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ADP7118ARDZ-5.0-R7
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Analog Devices Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownADP7118ARDZ-5.0-R7
Analog Devices · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8-EP
ADP7118ARDZ-5.0-R7 from Analog Devices, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Regulated output voltage; bypass VOUT to GND with a 2.2 µF or larger capacitor. |
| 2 | VOUT | power_out | Regulated output voltage; pin 2 is internally tied to pin 1 as a second VOUT pin, and VOUT should be bypassed to GND with a 2.2 µF or larger capacitor. |
| 3 | SENSE/ADJ | input | Sense input connected to the load; an external resistor divider can set the output above the fixed voltage (ADJ), and SENSE/ADJ to GND is rated −0.3 V to +6 V. |
| 4 | GND | power_in | Ground reference for the regulator. |
| 5 | EN | input | Enable input: high turns the regulator on and low shuts it down, with EN to GND rated −0.3 V to +24 V; connect EN to VIN for automatic startup. |
| 6 | SS | passive | Soft-start pin where an external capacitor sets the soft-start time; leave it open for the typical startup time and do not ground it, with SS rated −0.3 V to the lesser of VIN or +6 V. |
| 7 | VIN | power_in | Regulator input supply, operating from 2.7 V to 20 V and bypassed to GND with a 2.2 µF or larger capacitor; absolute maximum VIN to GND is −0.3 V to +24 V. |
| 8 | VIN | power_in | Regulator input supply, operating from 2.7 V to 20 V; pin 8 is internally tied to pin 7 as a second VIN pin. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage accuracy (initial) | VOUT | -0.8 | 0.8 | % | IOUT = 10 mA, TJ = 25°C | 3 | |
| Output voltage accuracy (line, load, temperature) | VOUT | -1.2 | 1.5 | % | 100 µA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +85°C | 3 | |
| Output voltage accuracy (line, load, temperature, full range) | VOUT | -1.8 | 1.8 | % | 100 µA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 20 V | 3 | |
| Input voltage range | VIN | 2.7 | 20 | V | 3 | ||
| Line regulation | ΔVOUT/ΔVIN | -0.015 | 0.015 | %/V | VIN = (VOUT + 1 V) to 20 V | 3 | |
| Load regulation | ΔVOUT/ΔIOUT | 0.002 | 0.004 | %/mA | ΔVOUT, IOUT = 100 µA to 200 mA | 3 | |
| Dropout voltage at 10 mA | VDROPOUT | 30 | 60 | mV | IOUT = 10 mA | 3 | |
| Dropout voltage at 200 mA | VDROPOUT | 200 | 420 | mV | IOUT = 200 mA | 3 | |
| Ground current at no load | IGND | 50 | 80 | µA | IOUT = 0 µA | 3 | |
| Ground current at 10 mA | IGND | 140 | 190 | µA | IOUT = 10 mA | 3 | |
| Ground current at 200 mA | IGND | 180 | 320 | µA | IOUT = 200 mA | 3 | |
| Shutdown current | IGND-SD | 10 | µA | EN = GND | 3 | ||
| Current limit threshold | ILIMIT | 250 | 360 | 460 | mA | Output voltage drops to 90% of nominal (footnote 4) | 3 |
| Precision EN input logic high threshold | ENHIGH | 1.15 | 1.22 | 1.3 | V | 2.7 V ≤ VIN ≤ 20 V | 3 |
| Precision EN input logic low threshold | ENLOW | 1.06 | 1.12 | 1.18 | V | 2.7 V ≤ VIN ≤ 20 V | 3 |
| EN input leakage current | IEN-LKG | 0.04 | 1 | µA | EN = VIN or GND | 3 | |
| SENSE input bias current | ISENSE-BIAS | 10 | 1000 | nA | 100 µA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 20 V | 3 | |
| Absolute max VIN to GND | VIN | -0.3 | 24 | V | VIN to GND | 5 | |
| Absolute max VOUT to GND | VOUT | -0.3 | V | VOUT to GND, maximum is VIN | 5 | ||
| Absolute max EN to GND | EN | -0.3 | 24 | V | EN to GND | 5 | |
| Absolute max SENSE/ADJ to GND | SENSE/ADJ | -0.3 | 6 | V | SENSE/ADJ to GND | 5 | |
| Absolute max SS to GND | SS | -0.3 | V | SS to GND, maximum is the lower of VIN or +6 V | 5 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 5 | ||
| Maximum junction temperature | TJ | 150 | °C | 5 | |||
| Operating ambient temperature range | TA | -40 | 125 | °C | 5 | ||
| Recommended output capacitance (input and output) | CMIN | 1.5 | µF | TA = −40°C to +125°C | 4 | ||
| Capacitor ESR | RESR | 0.001 | 0.3 | Ω | TA = −40°C to +125°C | 4 | |
| Recommended maximum junction temperature | TJ | 125 | °C | Junction temperature for reliable operation | 17 | ||
| Thermal resistance junction to ambient (8-lead SOIC) | θJA | 52.7 | °C/W | 4-layer board, worst case | 5 | ||
| Thermal resistance junction to case (8-lead SOIC) | θJC | 41.5 | °C/W | 5 | |||
| Thermal characterization parameter junction to board (8-lead SOIC) | ΨJB | 32.7 | °C/W | 5 | |||
| Thermal characterization parameter junction to board, typical (8-lead SOIC) | ΨJB | 38.8 | °C/W | 17 | |||
| Thermal shutdown threshold | TSSD | 150 | °C | 3 | |||
| Thermal shutdown hysteresis | TSSD-HYS | 15 | °C | 3 | |||
| Precision EN hysteresis | ENHYS | 100 | mV | 3 | |||
| Start-up time | tSTART-UP | 380 | µs | VOUT = 5 V; EN rising edge to 90% of VOUT | 3 | ||
| Output noise | OUTNOISE | 11 | µV rms | 10 Hz to 100 kHz, all output voltage options | 3 | ||
| Power supply rejection ratio at 10 kHz | PSRR | 88 | dB | 10 kHz, VIN = 7 V, VOUT = 5 V | 3 | ||
| Power supply rejection ratio at 100 kHz | PSRR | 68 | dB | 100 kHz, VIN = 7 V, VOUT = 5 V | 3 | ||
| Power supply rejection ratio at 1 MHz | PSRR | 50 | dB | 1 MHz, VIN = 7 V, VOUT = 5 V | 3 |
CAD (KiCad official)
- Symbol:
ADP7118ARDZ-5.0-R7 - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
adp7118ardz-5-0-r7-etched.step/adp7118ardz-5-0-r7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adp7118ardz-5-0-r7.step/adp7118ardz-5-0-r7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (23 pp, sha256
eec99b0f57a04ef6, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).