5PB1108PGGK from RENESAS, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CLKIN	input	LVCMOS clock input that is 3.3 V tolerant, with VIH minimum of 0.7 × VDD and VIL maximum of 0.3 × VDD.
2	1G	input	Output enable input: when high, the Yn outputs follow CLKIN; when low, the Yn outputs are held low (VIH minimum 2.0 V and VIL maximum 0.8 V at VDD = 3.3 V).
3	Y0	output	LVCMOS clock output with integrated 50 Ω serial termination, VOH minimum 2.4 V and VOL maximum 0.7 V at VDD = 3.3 V.
4	GND	power_in	Ground reference for the device.
5	VDD	power_in	Supply voltage of 1.71 V to 3.465 V, measured with respect to GND.
6	Y4	output	LVCMOS clock output with integrated 50 Ω serial termination, VOH minimum 2.4 V and VOL maximum 0.7 V at VDD = 3.3 V.
7	GND	power_in	Ground reference for the device.
8	Y6	output	LVCMOS clock output with integrated 50 Ω serial termination, VOH minimum 2.4 V and VOL maximum 0.7 V at VDD = 3.3 V.
9	Y7	output	LVCMOS clock output with integrated 50 Ω serial termination, VOH minimum 2.4 V and VOL maximum 0.7 V at VDD = 3.3 V.
10	VDD	power_in	Supply voltage of 1.71 V to 3.465 V, measured with respect to GND.
11	Y5	output	LVCMOS clock output with integrated 50 Ω serial termination, VOH minimum 2.4 V and VOL maximum 0.7 V at VDD = 3.3 V.
12	GND	power_in	Ground reference for the device.
13	Y2	output	LVCMOS clock output with integrated 50 Ω serial termination, VOH minimum 2.4 V and VOL maximum 0.7 V at VDD = 3.3 V.
14	VDD	power_in	Supply voltage of 1.71 V to 3.465 V, measured with respect to GND.
15	Y3	output	LVCMOS clock output with integrated 50 Ω serial termination, VOH minimum 2.4 V and VOL maximum 0.7 V at VDD = 3.3 V.
16	Y1	output	LVCMOS clock output with integrated 50 Ω serial termination, VOH minimum 2.4 V and VOL maximum 0.7 V at VDD = 3.3 V.

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	TSSOP-16
Category	Clock and Timing
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage, VDD	VDD			3.8	V		5
Output Enable and All Outputs		-0.4			V		5
Input Voltage, CLKIN		-0.4		3.465	V		5
Junction Temperature				125	°C		5
Ambient Operating Temperature (Extended and Automotive Grade 2)		-40		105	°C		5
Power Supply Voltage (measured in respect to GND)		1.71		3.465	V		5
Operating Voltage, VDD = 1.8V ±5% (Industrial and Extended)	VDD	1.71	1.8	1.89	V		7
Input High Voltage, 1G (VDD = 1.8V)	VIH	1.6			V		7
Input Low Voltage, 1G (VDD = 1.8V)	VIL			0.6	V		7
Output High Voltage (VDD = 1.8V)	VOH	1.4			V	I OH = -5mA.	7
Output Low Voltage (VDD = 1.8V)	VOL			0.4	V	I OL = 5mA.	7
Operating Supply Current, 5PB1108 (VDD = 1.8V)	IDD		20	23	mA	100MHz, no load, 25°C.	7
Input High Leakage (VDD = 1.8V)	IIH			5	µA	VIN = VDD	7
Input Low Leakage (VDD = 1.8V)	IIL			5	µA	VIN = 0V	7
Operating Voltage, VDD = 2.5V ±5% (Industrial and Extended)	VDD	2.375	2.5	2.625	V		9
Input High Voltage, 1G (VDD = 2.5V)	VIH	1.8			V		9
Input Low Voltage, 1G (VDD = 2.5V)	VIL			0.7	V		9
Output High Voltage (VDD = 2.5V)	VOH	1.9			V	I OH = -8mA.	9
Output Low Voltage (VDD = 2.5V)	VOL			0.5	V	I OL = 8mA.	9
Operating Supply Current, 5PB1108 (VDD = 2.5V)	IDD		27	31	mA	100MHz, no load, 25°C.	9
Input High Leakage (VDD = 2.5V)	IIH			5	µA	VIN = VDD	9
Input Low Leakage (VDD = 2.5V)	IIL			5	µA	VIN = 0V	9
Operating Voltage, VDD = 3.3V ±5% (Industrial and Extended)	VDD	3.135	3.3	3.465	V		11
Input High Voltage, 1G (VDD = 3.3V)	VIH	2			V		11
Input Low Voltage, 1G (VDD = 3.3V)	VIL			0.8	V		11
Output High Voltage (VDD = 3.3V)	VOH	2.4			V	I OH = -12mA.	11
Output Low Voltage (VDD = 3.3V)	VOL			0.7	V	I OL = 12mA.	11
Operating Supply Current, 5PB1108 (VDD = 3.3V)	IDD		35	38	mA	100MHz, no load, 25°C.	11
Input High Leakage (VDD = 3.3V)	IIH			5	µA	VIN = VDD	11
Input Low Leakage (VDD = 3.3V)	IIL			5	µA	VIN = 0V	11
Input Frequency (VDD = 1.8V)		0		200	MHz		13
Output Rise Time (2pF load, VDD = 1.8V)	tOR		0.5	0.75	ns	0.36V to 1.44V, CL = 2pF.	13
Output Fall Time (2pF load, VDD = 1.8V)	tOF		0.5	0.75	ns	1.44V to 0.36V, CL = 2pF.	13
Output Rise Time (5pF load, VDD = 1.8V)	tOR		0.8	1	ns	0.36V to 1.44V, CL = 5pF.	13
Output Fall Time (5pF load, VDD = 1.8V)	tOF		0.8	1	ns	1.44V to 0.36V, CL = 5pF.	13
Start-up Time (VDD = 1.8V)	tSTART-UP			3	ms	Part start-up time for valid outputs after VDD ramp-up.	13
Propagation Delay (VDD = 1.8V)	tPD		1.5	2.5	ns		13
Output to Output Skew, 5PB1108/10 (VDD = 1.8V)			45	65	ps	Rising edges at VDD/2.	13
Device to Device Skew (VDD = 1.8V)				200	ps	Rising edges at VDD/2.	13
Input Frequency (VDD = 2.5V)		0		200	MHz		15
Output Rise Time (2pF load, VDD = 2.5V)	tOR		0.4	0.7	ns	0.5V to 2.0V, CL = 2pF.	15
Output Fall Time (2pF load, VDD = 2.5V)	tOF		0.4	0.7	ns	2.0V to 0.5V, CL = 2pF.	15
Output Rise Time (5pF load, VDD = 2.5V)	tOR		0.75	1	ns	0.5V to 2.0V, CL = 5pF.	15
Output Fall Time (5pF load, VDD = 2.5V)	tOF		0.75	1	ns	2.0V to 0.5V, CL = 5pF.	15
Start-up Time (VDD = 2.5V)	tSTART-UP			3	ms	Part start-up time for valid outputs after VDD ramp-up.	15
Propagation Delay, 5PB1106/08 (VDD = 2.5V)	tPD		2	3.3	ns		15
Output to Output Skew, 5PB1108/10 (VDD = 2.5V)			45	65	ps	Rising edges at VDD/2.	15
Device to Device Skew (VDD = 2.5V)				200	ps	Rising edges at VDD/2.	15
Input Frequency (VDD = 3.3V)		0		200	MHz		17
Output Rise Time (2pF load, VDD = 3.3V)	tOR		0.45	0.6	ns	0.66V to 2.64V, CL = 2pF.	17
Output Fall Time (2pF load, VDD = 3.3V)	tOF		0.45	0.6	ns	2.64V to 0.66V, CL = 2pF.	17
Output Rise Time (5pF load, VDD = 3.3V)	tOR		0.7	1	ns	0.66V to 2.64V, CL = 5pF.	17
Output Fall Time (5pF load, VDD = 3.3V)	tOF		0.7	1	ns	2.64V to 0.66V, CL = 5pF.	17
Start-up Time (VDD = 3.3V)	tSTART-UP			3	ms	Part start-up time for valid outputs after VDD ramp-up.	17
Propagation Delay, 5PB1106/08 (VDD = 3.3V)	tPD		1.7	2.7	ns		17
Output to Output Skew, 5PB1108/10 (VDD = 3.3V)			45	65	ps	Rising edges at VDD/2.	17
Device to Device Skew (VDD = 3.3V)				200	ps	Rising edges at VDD/2.	17
Junction-to-Ambient Thermal Resistance, 16-TSSOP (5PB1108PGG)	ΘJA		80.9		°C/W	still air	6
Junction-to-Case Thermal Resistance, 16-TSSOP (5PB1108PGG)	ΘJC		43.3		°C/W	still air	6
Junction-to-Board Thermal Resistance, 16-TSSOP (5PB1108PGG)	ΘJB		60.1		°C/W	still air	6

CAD (KiCad official)

Symbol: 5PB1108PGGK
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: 5pb1108pggk-etched.step / 5pb1108pggk-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 5pb1108pggk.step / 5pb1108pggk.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (41 pp, sha256 a39aca2d9b003582, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

5PB1108PGGK

Verified 5PB1108PGGK

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README