component

HX9002-S

Public Made by Adom

by adom

ZHHXDZ Operational Amplifier, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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HX9002-S

ZHHXDZ · Operational Amplifier · SOP-8

HX9002-S from ZHHXDZ, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUTA output Output of amplifier A.
2 -INA input Inverting input of amplifier A; the voltage range is from (VS− − 0.1 V) to (VS+ + 0.1 V).
3 +INA input Non-inverting input of amplifier A; it has the same voltage range as −IN, from (VS− − 0.1 V) to (VS+ + 0.1 V).
4 -VS power_in Negative power supply (VS−); the device operates from 1.8 V to 5.5 V total supply at 0 to 70 ℃ and from 2.0 V to 5.5 V at −40 to +125 ℃.
5 +INB input Non-inverting input of amplifier B; it has the same voltage range as −IN, from (VS− − 0.1 V) to (VS+ + 0.1 V).
6 -INB input Inverting input of amplifier B; the voltage range is from (VS− − 0.1 V) to (VS+ + 0.1 V).
7 OUTB output Output of amplifier B.
8 +VS power_in Positive power supply (VS+); the device operates from 1.8 V to 5.5 V total supply at 0 to 70 ℃ and from 2.0 V to 5.5 V at −40 to +125 ℃.

Key specifications

Parameter Value
Manufacturer ZHHXDZ
Package SOP-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage VOS -2.5 0.5 2.5 mV 2
Input offset voltage over temperature VOS -2.8 2.8 mV TA = −40 to +125 ℃ 2
Offset voltage drift VOS TC 1 3 μV/℃ TA=−40 to +125 ℃ 2
Power supply rejection ratio PSRR 80 110 dB VS = 2.0 to 5.5 V, VCM < VS+ −2V 2
Power supply rejection ratio over temperature PSRR 75 dB TA = −40 to +125 ℃ 2
Common-mode rejection ratio CMRR 70 83 dB VS = 5.5 V, VCM = -0.1 to 5.6 V 3
Common-mode rejection ratio over temperature CMRR 65 dB VCM=0 to 5.3V, TA=−40 to +125℃ 3
Common-mode rejection ratio CMRR 65 77 dB VS = 2.0 V, VCM = −0.1 to 2.1 V 3
Common-mode rejection ratio over temperature CMRR 60 dB VCM=0 to 1.8V, TA=−40 to +125℃ 3
Open-loop voltage gain AVOL 90 105 dB RL = 25 kΩ, VO = 0.05 to 3.5 V 3
Open-loop voltage gain over temperature AVOL 85 dB TA = −40 to +125℃ 3
Open-loop voltage gain AVOL 85 100 dB RL = 2 kΩ, VO = 0.15 to 3.5 V 3
Open-loop voltage gain over temperature AVOL 80 dB TA = −40 to +125℃ 3
High output voltage swing (rail-relative, printed as VS+ − x) VOH 5 9 mV RL = 25 kΩ 3
High output voltage swing (rail-relative, printed as VS+ − x) VOH 63 95 mV RL = 2 kΩ 3
Low output voltage swing (rail-relative, printed as VS− + x) VOL 3.5 6 mV RL = 25 kΩ 3
Low output voltage swing (rail-relative, printed as VS− + x) VOL 43 65 mV RL = 2 kΩ 3
Operating supply voltage VS 1.8 5.5 V TA = 0 to +70℃ 3
Operating supply voltage VS 2 5.5 V TA = −40 to +125℃ 3
Quiescent current (per amplifier) IQ 75 125 μA 3
Quiescent current (per amplifier) over temperature IQ 160 μA TA = −40 to +125 ℃ 3
Supply voltage VS+ to VS− 10 V 2
Signal input terminals current -10 10 mA 2
Storage temperature range Tstg -65 150 ℃ 2
Junction temperature TJ 150 ℃ 2
Lead temperature range (soldering) 260 ℃ Soldering 10 sec 2
Operating temperature range TA -40 125 ℃ 3
Package thermal resistance SOP-8 θJA 125 ℃/W SOP-8 3
Input bias current IB 1 pA 2
Input bias current IB 150 pA TA = +85 ℃ 2
Input bias current IB 500 pA TA = +125 ℃ 2
Input offset current IOS 1 3
Input voltage noise (0.1 to 10 Hz) Vn 5.6 μVP-P f = 0.1 to 10 Hz 3
Input voltage noise density en 22 nV/√Hz f = 10 kHz 3
Input voltage noise density en 27 nV/√Hz f = 1 kHz 3
Input capacitance (differential) CIN 2 pF Differential 3
Input capacitance (common mode) CIN 3.5 pF Common mode 3
Gain bandwidth product GBW 1 MHz 3
Slew rate SR 1.2 V/μs G=+1, CL=100pF, VO=1.5 to 3.5V 3
Total harmonic distortion+noise THD+N 0.002 % G= +1, f=1 kHz, VO = 1VRMS 3
Settling time tS 1.2 μs To 0.1%, G = +1, 1V step 3
Settling time tS 1.5 μs To 0.01%, G = +1, 1V step 3
Overload recovery time tOR 2 To 0.1%, VIN * Gain > VS 3

CAD (KiCad official)

  • Symbol: HX9002-S
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: hx9002-s-etched.step / hx9002-s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hx9002-s.step / hx9002-s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ZHHXDZ datasheet (7 pp, sha256 fd0c615989aa4dc6, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF