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CYPD3171-24LQXQT
Public Made by Adomby adom
Cypress Semicon USB ICs, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCYPD3171-24LQXQT
Cypress Semicon · USB ICs · QFN-24-EP(4x4)
CYPD3171-24LQXQT from Cypress Semicon, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0 | bidirectional | Port 1 pin 0 GPIO, also alternate UART_1_CTS, I2C_SDA_1, and TCPWM_line_0, with programmable SCP/OCP/OVP/UVP fault indication. |
| 2 | P1.1 | bidirectional | Port 1 pin 1 GPIO, also alternate UART_1_RTS, I2C_SCL_1, and TCPWM_line_1, with programmable SCP/OCP/OVP/UVP fault indication. |
| 3 | VBUS_P_CTRL | tri_state | Provider (PMOS) FET gate control, 30-V tolerant: 0 = path ON, 1 = path OFF; the driver has an active pull-up and can drive high, low or High-Z. |
| 4 | VBUS_C_CTRL | tri_state | VBUS consumer (PMOS) FET gate control, 30-V tolerant: 0 = path ON, Z = path OFF; the driver can only drive low or High-Z and requires an external pull-up. |
| 5 | DP1/P1.2 | bidirectional | USB D+ for Port 1, also GPIO and UART_1_TX1, with AFC/QC/BC 1.2/Apple charging and No IEC functions. |
| 6 | DM1/P1.3 | bidirectional | USB D- for Port 1, also GPIO and UART_1_RX1, with AFC/QC/BC 1.2/Apple charging and No IEC functions. |
| 7 | SWD_DAT_0/P0.0 | bidirectional | SWD data line and Port 0 pin 0 GPIO (also OVT, I2C_SDA_0, TCPWM_line_0, UART_0_CTS), used for flash programming and debug. |
| 8 | SWD_CLK_0/P0.1 | input | SWD clock line and Port 0 pin 1 GPIO (also OVT, I2C_SCL_0, TCPWM_line_1, UART_0_RTS), used for flash programming and debug. |
| 9 | AXRES/P2.0 | bidirectional | Alternate XRES and Port 2 pin 0 GPIO (also TCPWM_line_0, UART_0_TX0); the pin is internally pulled up during Power-On I/O initialization. |
| 10 | P2.1 | bidirectional | Port 2 pin 1 GPIO, also alternate TCPWM_line_1 and UART_0_RX0. |
| 11 | VBUS_C_MON_DISCHARGE | passive | Type-C VBUS monitor with internal discharge FET; included in the VBUS short protection pins on the ESD list, and its specifications are in Tables 9 and 10. |
| 12 | P2.2 | bidirectional | Port 2 pin 2 GPIO with open-drain and pull-up assist, configurable as GPIO_20VT, I2C_SDA_1, or IEC; tolerant to temporary short to VBUS. |
| 13 | P2.3 | bidirectional | Port 2 pin 3 GPIO with open-drain and pull-up assist, configurable as GPIO_20VT, I2C_SCL_1, or IEC; tolerant to temporary short to VBUS. |
| 14 | CC2 | bidirectional | Type-C communication channel 2 with dead-battery Rd bonding option and IEC protection; tolerant to temporary short to VBUS. |
| 15 | CC1 | bidirectional | Type-C communication channel 1 with dead-battery Rd bonding option and IEC protection; tolerant to temporary short to VBUS. |
| 16 | DM0/P3.1 | bidirectional | USB D- for Port 3, also Port 3 pin 1 GPIO and UART_1_RX0, with AFC/QC/BC 1.2/Apple charging and IEC functions. |
| 17 | DP0/P3.0 | bidirectional | USB D+ for Port 3, also Port 3 pin 0 GPIO and UART_1_TX0, with AFC/QC/BC 1.2/Apple charging and IEC functions. |
| 18 | VBUS_IN_DISCHARGE | power_in | VBUS power input, 3.0 V to 24.5 V, with internal discharge FET; this pin is not supported as a power supply output. |
| 19 | CSP | input | Current sense amplifier positive input (CS+) for the low-side current sense amplifier. |
| 20 | FB | input | Voltage regulation feedback pin for the integrated VBUS regulation circuitry. |
| 21 | CATH/COMP | passive | Cathode of voltage regulation and compensation pin for other applications. |
| 22 | GND | power_in | Ground. |
| 23 | VDDD | power_in | Power input, 2.7 V to 5.5 V; when powered from VBUS_IN_DISCHARGE it is a 3.3-V regulator output that should be decoupled with 1 µF. |
| 24 | VCCD | passive | 1.8-V core voltage pin, not intended for use as a power source. |
| 25 | EPAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Cypress Semicon |
| Package | QFN-24-EP(4x4) |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Max supply voltage relative to VSS on VBUS_IN_DISCHARGE and VBUS_C_MON_DISCHARGE pins | VBUS_MAX | 30 | V | Absolute max | 17 | ||
| Max supply voltage relative to VSS | VDDD_MAX | 6 | V | 17 | |||
| Max voltage on CC1, CC2 pins and port pins P2.2 and P2.3 for applicable devices | VCC_PIN_ABS | 22 | V | 17 | |||
| GPIO voltage | VGPIO_ABS | -0.5 | V | 17 | |||
| Maximum current per GPIO | IGPIO_ABS | -25 | 25 | mA | 17 | ||
| GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS | IGPIO_injection | -0.5 | 0.5 | mA | Absolute max, current injected per pin | 17 | |
| OVT GPIO voltage | VGPIO_OVT_ABS | -0.5 | 6 | V | Applicable to port pins P0.0 and P0.1 | 17 | |
| Electrostatic discharge human body model | ESD_HBM | 2200 | V | 17 | |||
| Electrostatic discharge charged device model | ESD_CDM | 500 | V | 17 | |||
| Pin current for latch-up | LU | -100 | 100 | mA | 17 | ||
| Electrostatic discharge IEC61000-4-2 contact discharge | ESD_IEC_CON | 8000 | V | Contact discharge on CC1, CC2, VBUS, P2.2 and P2.3 pins | 17 | ||
| Electrostatic discharge IEC61000-4-2 air discharge | ESD_IEC_AIR | 15000 | V | Air discharge for DPLUS, DMINUS, CC1, CC2, VBUS, P2.2 and P2.3 pins | 17 | ||
| VDDD Power Supply Input Voltage | VDDD | 2.7 | 5.5 | V | Sink mode, -40 °C to 105 °C TA | 17 | |
| VDDD Power Supply Input Voltage | VDDD | 3 | 5.5 | V | Source mode, -40 °C to 105 °C TA | 17 | |
| VBUS_IN Power Supply Input Voltage | VBUS_IN | 3 | 24.5 | V | -40 °C to 105 °C TA | 17 | |
| Power supply decoupling capacitor for VDDD | Cexc | 0.8 | 1 | µF | X5R ceramic or better | 17 | |
| CPU input frequency | FCPU | 48 | MHz | All VDDD | 18 | ||
| Wakeup from Deep Sleep mode | TDEEPSLEEP | 35 | µs | 18 | |||
| Power-up to Ready to accept I2C/CC command | T_PWR_RDY | 5 | 25 | ms | 18 | ||
| Total startup time for the regulator supply outputs | Tstart | 200 | µs | Guaranteed by Characterization. | 28 | ||
| Integral non-linearity | INL | -2.5 | 2.5 | LSB | Reference voltage generated from VDDD | 28 | |
| Integral non-linearity | INL | -1.5 | 1.5 | LSB | Reference voltage generated from bandgap | 28 | |
| Differential non-linearity | DNL | -2.5 | 2.5 | LSB | Reference voltage generated from VDDD | 28 | |
| Differential non-linearity | DNL | -1.5 | 1.5 | LSB | Reference voltage generated from bandgap | 28 | |
| Gain error | Gain Error | -1.5 | 1.5 | LSB | 28 | ||
| ADC reference voltage when generated from band gap. | VREF_ADC2 | 1.96 | 2 | 2.04 | V | Reference voltage generated from bandgap | 28 |
| Rate of change of sampled voltage signal | SLEW_Max | 3 | V/ms | 28 | |||
| Row erase time | FLASH_ERASE | 15.5 | ms | -40 °C to 85 °C TA, all VDDD | 28 | ||
| Row (Block) write time (erase and program) | FLASH_WRITE | 20 | ms | -40 °C to 85 °C TA, all VDDD | 28 | ||
| Row program time after erase | FLASH_ROW_PGM | 7 | ms | 25 °C to 55 °C TA, all VDDD | 28 | ||
| Bulk erase time (32 KB) | TBULKERASE | 35 | ms | 28 | |||
| Total device program time | TDEVPROG | 7.5 | s | 28 | |||
| Flash retention | FRET1 | 20 | years | TA up to 55 °C, 100K P/E cycles | 28 | ||
| Flash retention | FRET2 | 10 | years | TA up to 85 °C, 10K P/E cycles | 28 | ||
| Flash retention | FRET3 | 3 | years | TA up to 105 °C, 10K P/E cycles | 28 | ||
| Operating ambient temperature | TA | -40 | 25 | 105 | °C | Extended Industrial | 30 |
| Operating junction temperature | TJ | -40 | 25 | 120 | °C | Extended Industrial | 30 |
| Package junction-to-ambient thermal resistance (24-QFN) | TJA | 19.98 | °C/W | 30 | |||
| Package junction-to-case thermal resistance (24-QFN) | TJC | 4.78 | °C/W | 30 |
CAD (KiCad official)
- Symbol:
CYPD3171-24LQXQT - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: QFN-24-EP(4x4), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.6 mm tall, datasheet A, max). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
- 3D model files:
cypd3171-24lqxqt-etched.step/cypd3171-24lqxqt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cypd3171-24lqxqt.step/cypd3171-24lqxqt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Cypress Semicon datasheet (37 pp, sha256
0cb40f06747905a6, retrieved 2026-11-12, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).