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TMDS261BPAG

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Texas Instruments Video Interface ICs, TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TMDS261BPAG

Texas Instruments · Video Interface ICs · TQFP-64(10x10)

TMDS261BPAG from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No-connect pin; leave unconnected.
2 NC unconnected No-connect pin; leave unconnected.
3 GND power_in Ground pin for the device.
4 NC unconnected No-connect pin; leave unconnected.
5 NC unconnected No-connect pin; leave unconnected.
6 VCC power_in 3.3-V supply pin for the TMDS circuitry, HPD, DDC and most of the control logic.
7 NC unconnected No-connect pin; leave unconnected.
8 NC unconnected No-connect pin; leave unconnected.
9 GND power_in Ground pin for the device.
10 NC unconnected No-connect pin; leave unconnected.
11 NC unconnected No-connect pin; leave unconnected.
12 VCC power_in 3.3-V supply pin for the TMDS circuitry, HPD, DDC and most of the control logic.
13 NC unconnected No-connect pin; leave unconnected.
14 NC unconnected No-connect pin; leave unconnected.
15 GND power_in Ground pin for the device.
16 VSadj input TMDS-compliant voltage swing control; a 4.02 kΩ ±10% resistor is selected to pass voltage HDMI compliance.
17 D2+_SINK output Sink-side TMDS data channel 2 positive differential output.
18 D2-_SINK output Sink-side TMDS data channel 2 negative differential output.
19 VCC power_in 3.3-V supply pin for the TMDS circuitry, HPD, DDC and most of the control logic.
20 D1+_SINK output Sink-side TMDS data channel 1 positive differential output.
21 D1-_SINK output Sink-side TMDS data channel 1 negative differential output.
22 GND power_in Ground pin for the device.
23 D0+_SINK output Sink-side TMDS data channel 0 positive differential output.
24 D0-_SINK output Sink-side TMDS data channel 0 negative differential output.
25 VCC power_in 3.3-V supply pin for the TMDS circuitry, HPD, DDC and most of the control logic.
26 CLK+_SINK output TMDS sink-side differential clock positive output.
27 CLK-_SINK output TMDS sink-side differential clock negative output.
28 GND power_in Ground pin for the device.
29 SCL_SINK bidirectional TMDS sink-side bidirectional DDC clock.
30 SDA_SINK bidirectional TMDS sink-side bidirectional DDC data.
31 HPD_SINK input Sink hot-plug-detect input; in standby mode HPD1 and HPD2 follow this pin.
32 S1/SCL input Source select 1 (GPIO mode) or local I2C clock (I2C mode), selected by the I2C_SEL pin.
33 S2/SDA bidirectional Source select 2 (GPIO mode) or local I2C data (I2C mode), selected by the I2C_SEL pin.
34 I2C_SEL input GPIO/local I2C control select: High configures the device by GPIO logic, Low configures it by I2C logic.
35 HPD1 output Source port 1 hot-plug-detect output.
36 SDA1 bidirectional Port-1 TMDS bidirectional DDC data.
37 SCL1 bidirectional Port-1 TMDS bidirectional DDC clock.
38 CLK-_1 input Port-1 TMDS differential clock negative input.
39 CLK+_1 input Port-1 TMDS differential clock positive input.
40 VCC power_in 3.3-V supply pin for the TMDS circuitry, HPD, DDC and most of the control logic.
41 D0-_1 input Port-1 TMDS differential data 0 negative input.
42 D0+_1 input Port-1 TMDS differential data 0 positive input.
43 GND power_in Ground pin for the device.
44 D1-_1 input Port-1 TMDS differential data 1 negative input.
45 D1+_1 input Port-1 TMDS differential data 1 positive input.
46 VCC power_in 3.3-V supply pin for the TMDS circuitry, HPD, DDC and most of the control logic.
47 D2-_1 input Port-1 TMDS differential data 2 negative input.
48 D2+_1 input Port-1 TMDS differential data 2 positive input.
49 LP input Low-power select bar: High selects normal operation, Low forces the device into the low-power state.
50 HPD2 output Source port 2 hot-plug-detect output.
51 SDA2 bidirectional Port-2 TMDS bidirectional DDC data.
52 SCL2 bidirectional Port-2 TMDS bidirectional DDC clock.
53 CLK-_2 input Port-2 TMDS differential clock negative input.
54 CLK+_2 input Port-2 TMDS differential clock positive input.
55 VCC power_in 3.3-V supply pin for the TMDS circuitry, HPD, DDC and most of the control logic.
56 D0-_2 input Port-2 TMDS differential data 0 negative input.
57 D0+_2 input Port-2 TMDS differential data 0 positive input.
58 GND power_in Ground pin for the device.
59 D1-_2 input Port-2 TMDS differential data 1 negative input.
60 D1+_2 input Port-2 TMDS differential data 1 positive input.
61 VCC power_in 3.3-V supply pin for the TMDS circuitry, HPD, DDC and most of the control logic.
62 D2-_2 input Port-2 TMDS differential data 2 negative input.
63 D2+_2 input Port-2 TMDS differential data 2 positive input.
64 NC unconnected No-connect pin; leave unconnected.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category Interface
Pins 64

CAD (KiCad official)

  • Symbol: TMDS261BPAG
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: tmds261bpag-etched.step / tmds261bpag-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tmds261bpag.step / tmds261bpag.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (50 pp, sha256 04744a4640e5eb60, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF