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ADC3421IRTQT

Texas Instruments · Analog To Digital Converters (ADC) · QFN-56-EP(8x8)

ADC3421IRTQT from Texas Instruments, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DA1P output Positive serial LVDS output for wire-1 of channel A; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
2 DA1M output Negative serial LVDS output for wire-1 of channel A; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
3 DA0P output Positive serial LVDS output for wire-0 of channel A; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
4 DA0M output Negative serial LVDS output for wire-0 of channel A; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
5 DVDD power_in Digital 1.8-V power supply; recommended range 1.7 V to 1.9 V.
6 AVDD power_in Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
7 AVDD power_in Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
8 INAM input Negative differential analog input for channel A; input common-mode is VCM ± 0.025 V.
9 INAP input Positive differential analog input for channel A; input common-mode is VCM ± 0.025 V.
10 AVDD power_in Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
11 AVDD power_in Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
12 INBP input Positive differential analog input for channel B; input common-mode is VCM ± 0.025 V.
13 INBM input Negative differential analog input for channel B; input common-mode is VCM ± 0.025 V.
14 AVDD power_in Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
15 AVDD power_in Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
16 SCLK input Serial interface clock input with an internal 150-kΩ pulldown; absolute maximum is 3.9 V.
17 SDATA input Serial interface data input with an internal 150-kΩ pulldown; absolute maximum is 3.9 V.
18 SEN input Serial interface enable, active low, with an internal 150-kΩ pullup to AVDD; absolute maximum is 3.9 V.
19 SDOUT output Serial interface data output.
20 AVDD power_in Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
21 CLKM input Negative differential clock input for the ADC; input clock amplitude is 0.2 to 1.5 VPP for sine wave (ac-coupled) and common-mode is 0.95 V.
22 CLKP input Positive differential clock input for the ADC; input clock amplitude is 0.2 to 1.5 VPP for sine wave (ac-coupled) and common-mode is 0.95 V.
23 AVDD power_in Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
24 RESET input Hardware reset, active high, with an internal 150-kΩ pulldown; absolute maximum is 3.9 V.
25 SYSREFP input Positive external SYSREF input; absolute range is -0.3 V to AVDD + 0.3 V.
26 SYSREFM input Negative external SYSREF input; absolute range is -0.3 V to AVDD + 0.3 V.
27 VCM output Common-mode voltage for analog inputs, nominally 0.95 V.
28 AVDD power_in Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
29 AVDD power_in Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
30 INCM input Negative differential analog input for channel C; input common-mode is VCM ± 0.025 V.
31 INCP input Positive differential analog input for channel C; input common-mode is VCM ± 0.025 V.
32 AVDD power_in Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
33 AVDD power_in Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
34 INDP input Positive differential analog input for channel D; input common-mode is VCM ± 0.025 V.
35 INDM input Negative differential analog input for channel D; input common-mode is VCM ± 0.025 V.
36 AVDD power_in Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
37 PDN input Power-down control, configurable via SPI, with an internal 150-kΩ pulldown; absolute maximum is 3.9 V.
38 DVDD power_in Digital 1.8-V power supply; recommended range 1.7 V to 1.9 V.
39 DD1P output Positive serial LVDS output for wire-1 of channel D; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
40 DD1M output Negative serial LVDS output for wire-1 of channel D; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
41 DD0P output Positive serial LVDS output for wire-0 of channel D; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
42 DD0M output Negative serial LVDS output for wire-0 of channel D; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
43 DC1P output Positive serial LVDS output for wire-1 of channel C; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
44 DC1M output Negative serial LVDS output for wire-1 of channel C; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
45 DC0P output Positive serial LVDS output for wire-0 of channel C; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
46 DC0M output Negative serial LVDS output for wire-0 of channel C; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
47 DVDD power_in Digital 1.8-V power supply; recommended range 1.7 V to 1.9 V.
48 FCLKP output Positive frame clock output; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
49 FCLKM output Negative frame clock output; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
50 DCLKP output Positive bit clock output; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
51 DCLKM output Negative bit clock output; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
52 DVDD power_in Digital 1.8-V power supply; recommended range 1.7 V to 1.9 V.
53 DB1P output Positive serial LVDS output for wire-1 of channel B; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
54 DB1M output Negative serial LVDS output for wire-1 of channel B; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
55 DB0P output Positive serial LVDS output for wire-0 of channel B; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
56 DB0M output Negative serial LVDS output for wire-0 of channel B; the single-ended load is specified as 100 Ω with at most 3.3 pF from each output pin to GND.
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-56-EP(8x8)
Category Data Acquisition
Pins 57

CAD (KiCad official)

  • Symbol: ADC3421IRTQT
  • Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • 3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: adc3421irtqt-etched.step / adc3421irtqt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adc3421irtqt.step / adc3421irtqt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (80 pp, sha256 48d3d273984a8052, retrieved 2026-10-12, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF