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SN65LVDT9637BDR
Public Made by Adomby adom
Texas Instruments LVDS ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN65LVDT9637BDR
Texas Instruments · LVDS ICs · SOIC-8
SN65LVDT9637BDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Supply pin for the 3.3 V device, specified at 3 V to 3.6 V with an absolute maximum of -0.5 V to 4 V, and a 0.1-µF capacitor should be placed as close to the device terminals as possible. |
| 2 | 1Y | output | Receiver 1 output that goes high for VID ≥ -32 mV and low for VID ≤ -100 mV, with VOH of 2.4 V min at IOH = -4 mA and VOL of 0.4 V max at IOL = 4 mA. |
| 3 | 2Y | output | Receiver 2 output that goes high for VID ≥ -32 mV and low for VID ≤ -100 mV, with VOH of 2.4 V min at IOH = -4 mA and VOL of 0.4 V max at IOL = 4 mA. |
| 4 | GND | power_in | Network ground terminal to which all non-differential voltages on the device are referenced. |
| 5 | 2B | input | Inverting differential input of receiver 2, rated for bus voltage of -2 V to 4.4 V (absolute range -4 V to 6 V) and for input current limits given in the electrical characteristics. |
| 6 | 2A | input | Non-inverting differential input of receiver 2, rated for bus voltage of -2 V to 4.4 V (absolute range -4 V to 6 V), with a differential input magnitude of 0.1 V to 3 V for the LVDS version and 0.8 V for the LVDT version. |
| 7 | 1B | input | Inverting differential input of receiver 1, rated for bus voltage of -2 V to 4.4 V (absolute range -4 V to 6 V) and for input current limits given in the electrical characteristics. |
| 8 | 1A | input | Non-inverting differential input of receiver 1, rated for bus voltage of -2 V to 4.4 V (absolute range -4 V to 6 V), with a differential input magnitude of 0.1 V to 3 V for the LVDS version and 0.8 V for the LVDT version. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Interface |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
SN65LVDT9637BDR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
sn65lvdt9637bdr-etched.step/sn65lvdt9637bdr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn65lvdt9637bdr.step/sn65lvdt9637bdr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
a6fe6aaf7a83af37, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).