TPS65287RHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RLIM3	input	Current limit setting for Buck3; a resistor to ground sets the peak current limit on the output inductor.
2	SS3	input	Soft start pin for Buck3; a small ceramic capacitor sets the converter soft start time.
3	COMP3	output	Compensation for Buck3; a series RC circuit completes the converter compensation.
4	FB3	input	Feedback pin for Buck3; connect a divider set to 0.8 V from the converter output to ground.
5	PB_IN	input	Push button input (active low).
6	ROSC	input	Oscillator set; the resistor sets the frequency of the internal autonomous clock.
7	FB1	input	Feedback pin for Buck1; connect a divider set to 0.8 V from the converter output to ground.
8	COMP1	output	Compensation pin for Buck1; a series RC circuit completes the converter compensation.
9	SS1	input	Soft-start pin for Buck1; a small ceramic capacitor sets the converter soft-start time.
10	RLIM1	input	Current limit setting pin for Buck1; a resistor to ground sets the peak current limit on the output inductor.
11	EN1	input	Enable pin for Buck1; a high signal enables the regulator, and a small capacitor to ground adds delayed start-up.
12	BST1	passive	Bootstrap capacitor for Buck1; fit a 47-nF ceramic capacitor from this pin to the switching node.
13	VIN1	power_in	Input supply for Buck1; fit a 10-µF ceramic capacitor close to this pin.
14	LX1	output	Switching node for Buck1.
15	LX1	output	Switching node for Buck1.
16	LX2	output	Switching node for Buck2.
17	LX2	output	Switching node for Buck2.
18	VIN2	power_in	Input supply for Buck2; fit a 10-µF ceramic capacitor close to this pin.
19	BST2	passive	Bootstrap capacitor for Buck2; fit a 47-nF ceramic capacitor from this pin to the switching node.
20	EN2	input	Enable pin for Buck2; a high signal enables the regulator, and a small capacitor to ground adds delayed start-up.
21	RLIM2	input	Current limit setting pin for Buck2; a resistor to ground sets the peak current limit on the output inductor.
22	SS2	input	Soft-start pin for Buck2; a small ceramic capacitor sets the converter soft-start time.
23	COMP2	output	Compensation pin for Buck2; a series RC circuit completes the converter compensation.
24	FB2	input	Feedback input for Buck2; connect a divider set to 0.8 V from the converter output to ground.
25	F_PWM	input	Forces PWM operation in all converters when high; when low the converters operate in automatic PFM/PWM mode.
26	INT	output	Open drain interrupt output.
27	PGOOD	output	Power good open drain output, asserted after all converters are sequenced and within regulation; polarity is factory selectable (active high default).
28	V7V	power_out	Internal supply; connect a 4.7-µF to 10-µF ceramic capacitor from this pin to ground.
29	V3V	power_out	Internal supply; connect a 3.3-µF to 10-µF ceramic capacitor from this pin to ground.
30	RSET	input	Sets the USB current limit by an external resistor to ground; connect to ground for the default 1.2 A limit.
31	IC	input	This pin should be connected to the V7V pin.
32	USB_VIN	power_in	USB switch input supply.
33	USB_VO	power_out	USB switch output.
34	USB_EN	input	Enable input for the USB switch; high turns on the switch.
35	USB_nFAULT	output	USB fault flag output, open drain, active low, asserted when an overcurrent or overtemperature condition is detected in the switch.
36	LX3	output	Switching node for Buck3.
37	LX3	output	Switching node for Buck3.
38	VIN3	power_in	Input supply for Buck3; fit a 10-µF ceramic capacitor close to this pin.
39	BST3	passive	Bootstrap capacitor for Buck3; fit a 47-nF ceramic capacitor from this pin to the switching node.
40	EN3	input	Enable pin for Buck3; a high signal enables the converter, and a small capacitor to ground adds delayed start-up.
41	PowerPAD	power_in	PowerPAD; connect to system ground for electrical and thermal connection.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-40-EP(6x6)
Category	Power Management ICs
Pins	41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Voltage range at VIN1, VIN2, VIN3, LX1, LX2, LX3		-0.3		20	V		7
Voltage range at LX1, LX2, LX3 (transient <10 ns)		-3		20	V	maximum withstand voltage transient < 10 ns	7
BST1/2/3 voltage referenced to LX		-0.3		7	V		7
Voltage at V7V, COMPx, USB_VIN, USB_VO, USB_EN, USB_nFAULT, PB_IN, INT, PGOOD		-0.3		7	V		7
Voltage at V3V, RLIMx, ENx, SSx, FBx, ROSC, F_PWM, RSET		-0.3		3.6	V		7
Voltage at GND		-0.3		0.3	V		7
Operating junction temperature range	TJ	-40		125	°C		7
Storage temperature range	TSTG	-55		150	°C		7
Input operating voltage	VIN	4.5		18	V		7
Junction temperature (labelled TA)	TA	-40		85	°C		7
ESD HBM, PB_IN pin to ground				2000	V	Human body model, PB_IN pin to ground	7
ESD CDM				500	V	Charge device model	7
Junction-to-ambient thermal resistance, RHA	θJA		30		°C/W	JEDEC 51.5 high K board	7
Input voltage range	VIN	4.5		18	V		8
Shutdown current	IDDSDN			180	µA	EN pin = low for all converters	8
Quiescent current, converters enabled, no load	IDDQ			700	µA	Converters enabled, no load, Buck1=1.2 V, Buck2=1.8 V, Buck3=3.3 V, TA=25°C, F_PWM=Low (push-button pull-up current not included)	8
Quiescent current, forced PWM	IDDQ		24		mA	Converters enabled, no load, F_PWM = High	8
VIN UVLO rising	UVLO		4.22		V	Rising VIN	8
VIN UVLO falling	UVLO		4.1		V	Falling VIN	8
UVLO deglitch	UVLODEGLITCH		110		µs	Both edges	8
Internal biasing supply	V3p3		3.3		V		8
Internal biasing supply	V7V		6.25		V		8
V7V UVLO rising	V7VUVLO		3.8		V	Rising V7V	8
V7V UVLO falling	V7VUVLO		3.6		V	Falling V7V	8
V7V UVLO deglitch	V7VUVLO_DEGLITCH		120		µs	Falling edge	8
Enable threshold high (x V3p3)	VIH_ENx		0.66		V	V3p3 = 3.2 V - 3.4 V, VENx rising; value is 0.66 x V3p3	8
Enable threshold low (x V3p3)	VIL_ENx		0.33		V	V3p3 = 3.2 V - 3.4 V, VENx falling; value is 0.33 x V3p3	8
Pull up current enable pin	ICHEN		4		µA		8
Discharge time enable pins	tD		10		ms	Power-up	8
Soft-start pin current source	ISS		5		µA		8
Converter switching frequency range	FSW_BK	0.3		2.2	MHz	Set externally with resistor	8
Internal oscillator accuracy	fSW_TOL	-10		10	%	fSW = 800 kHz	8
Feedback voltage	VFB	-1	0.8	1	V	VIN = 12 V, TA = 25°C (tolerance in %)	8
Feedback voltage	VFB	-2	0.8	2	V	VIN = 4.5 V to 16 V (tolerance in %)	8
Minimum on time	tON_MIN		135		ns	current sense blanking	8
Peak inductor current limit range Buck1	ILIMIT1	0.75		4	A		8
Peak inductor current limit range Buck2	ILIMIT2	0.75		3	A		8
Peak inductor current limit range Buck3	ILIMIT3	0.75		3	A		8
High side FET on resistance CH1	RDS(on)		95		mΩ	H.S. Switch 25°C, BOOT = 6.5 V	8
Low side FET on resistance CH1	RDS(on)		50		mΩ	L.S. Switch 25°C, VIN = 12 V	8
High side FET on resistance CH2	RDS(on)		120		mΩ	H.S. Switch 25°C, BOOT = 6.5 V	9
Low side FET on resistance CH2	RDS(on)		80		mΩ	L.S. Switch 25°C, VIN = 12 V	9
High side FET on resistance CH3	RDS(on)		120		mΩ	H.S. Switch 25°C, BOOT = 6.5 V	9
Low side FET on resistance CH3	RDS(on)		80		mΩ	L.S. Switch 25°C, VIN = 12 V	9
Error amplifier transconductance	gM		130		µS	-2 µA < ICOMP < 2 µA	9
Buck UV threshold, output falling	VUVBUCKX		85		%	Output falling	9
Buck UV threshold, output rising	VUVBUCKX		90		%	Output rising (PG will be asserted)	9
Power good deglitch time	tUV_deglitch		11		ms	both edges	9
Hiccup mode ON time	tON_HICCUP		14		ms	VUVBUCKX asserted	9
Hiccup mode OFF time	tOFF_HICCUP		20		ms	All converters disabled	9
Buck OV threshold, output rising	VOVBUCKX		106		%	Output rising (high side FET will be forced off)	9
Buck OV threshold, output falling	VOVBUCKX		104		%	Output falling (high side FET will be allowed to switch)	9
Minimum reset period	tRP		100		ms	Measured after the later of Buck1 or Buck3 power-up successfully	9
PB_IN internal de-bounce time	TPB_DEGLITCH		20		ms	turn_on and turn_off	9
USB input voltage range	VINUSB	2.5		6	V		9
USB switch static on-state resistance	RDS_USB		135		mΩ	USB_VIN = 5 V and Io_USB = 0.5 A, TJ = 25°C	9
USB current limit threshold	IOS	1.65	1.76	1.87	A	RSET = 25 kΩ	9
USB current limit threshold	IOS	1.18	1.26	1.34	A	RSET = 40 kΩ	9
USB current limit threshold	IOS	0.47	0.5	0.53	A	RSET = 90 kΩ	9
USB_nFAULT output voltage low	VUSB_nFAULT			150	mV	IUSB_nFAULT = 1 mA	9
USB turn-on delay time	TD_on		1.1		ms	USB_IN = 5 V, CL = 10 µF, RL = 100 Ω	10
USB turn-off delay time	TD_off		1.6		ms	USB_IN = 5 V, CL = 10 µF, RL = 100 Ω	10
USB response time to short circuit	TIOS		2		µs	USB_IN = 5 V	10
Switch over current fault deglitch	TDEGLITCH(OCP)		8.8		ms	Fault assertion or de-assertion due to over-current condition	10
USB discharge resistance	RDIS		130		Ω	USB_IN = 5 V, USB_EN = 0 V	10
USB thermal trip point	TUSB_TRIP		130		°C	Rising temperature	10
USB thermal trip hysteresis	TUSB_HYST		20		°C	Hysteresis	10
Thermal shutdown trip point	TTRIP		160		°C	Rising temperature	10
Thermal shutdown hysteresis	THYST		20		°C	Device re-starts	10

CAD (KiCad official)

Symbol: TPS65287RHAR
Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
3D model files: tps65287rhar-etched.step / tps65287rhar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps65287rhar.step / tps65287rhar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (34 pp, sha256 7e1011498480df3d, retrieved 2026-10-31, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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TPS65287RHAR

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