ADG3308BCBZ-1-RL7 from Analog Devices, in a WLCSP-20(2x2.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
a4	VCCA	power_in	Power supply input for the A1 to A8 I/O pins (1.15 V ≤ VCCA < VCCY).
a3	A1	bidirectional	Input/Output A1, referenced to VCCA.
b4	A2	bidirectional	Input/Output A2, referenced to VCCA.
b3	A3	bidirectional	Input/Output A3, referenced to VCCA.
c4	A4	bidirectional	Input/Output A4, referenced to VCCA.
c3	A5	bidirectional	Input/Output A5, referenced to VCCA.
d4	A6	bidirectional	Input/Output A6, referenced to VCCA.
d3	A7	bidirectional	Input/Output A7, referenced to VCCA.
e4	A8	bidirectional	Input/Output A8, referenced to VCCA.
e3	EN	input	Active-high enable input, referenced to VCCA on the ADG3308-1; EN low puts all A and Y pins in high impedance.
e2	GND	power_in	Ground.
e1	Y8	bidirectional	Input/Output Y8, referenced to VCCY.
d2	Y7	bidirectional	Input/Output Y7, referenced to VCCY.
d1	Y6	bidirectional	Input/Output Y6, referenced to VCCY.
c2	Y5	bidirectional	Input/Output Y5, referenced to VCCY.
c1	Y4	bidirectional	Input/Output Y4, referenced to VCCY.
b2	Y3	bidirectional	Input/Output Y3, referenced to VCCY.
b1	Y2	bidirectional	Input/Output Y2, referenced to VCCY.
a2	Y1	bidirectional	Input/Output Y1, referenced to VCCY.
a1	VCCY	power_in	Power supply input for the Y1 to Y8 I/O pins (1.65 V ≤ VCCY ≤ 5.5 V).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	WLCSP-20(2x2.5)
Category	Logic ICs
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
A side output low voltage	VOLA			0.4	V	VY = 0 V, IOL = 20 μA	3
Y side output low voltage	VOLY			0.4	V	VA = 0 V, IOL = 20 μA	3
A side high-Z leakage current	ILA, HIGH-Z	-1		1	μA	VA = 0 V or VCCA, EN = 0	3
Y side high-Z leakage current	ILY, HIGH-Z	-1		1	μA	VY = 0 V or VCCY, EN = 0	3
EN leakage current	ILEN	-1		1	μA	VEN = 0 V or VCCY, VA = 0 V	3
A side capacitance	CA		10		pF	f = 1 MHz, EN = 0	3
Y side capacitance	CY		6.8		pF	f = 1 MHz, EN = 0	3
EN capacitance	CEN		4.5		pF		3
Enable time	tEN		1	1.8	μs	RS = RT = 50 Ω	3
Power supply voltage VCCA	VCCA	1.15		5.5	V	VCCA ≤ VCCY	5
Power supply voltage VCCY	VCCY	1.65		5.5	V		5
Quiescent supply current VCCA	ICCA		0.17	1	μA	VA = 0 V or VCCA, VY = 0 V or VCCY, VCCA = VCCY = 5.5 V, EN = VCCY	5
Quiescent supply current VCCY	ICCY		0.27	1	μA	VA = 0 V or VCCA, VY = 0 V or VCCY, VCCA = VCCY = 5.5 V, EN = VCCY	5
Three-state supply current VCCA	IHIGH-ZA		0.1	1	μA	VCCA = VCCY = 5.5 V, EN = 0	5
Three-state supply current VCCY	IHIGH-ZY		0.1	1	μA	VCCA = VCCY = 5.5 V, EN = 0	5
Maximum data rate A→Y	DMAX, A→Y	50			Mbps	3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, CL = 50 pF	3
Maximum data rate Y→A	DMAX, Y→A	50			Mbps	3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, CL = 15 pF	3
Maximum data rate A→Y	DMAX, A→Y	50			Mbps	1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, CL = 50 pF	4
Maximum data rate Y→A	DMAX, Y→A	50			Mbps	1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, CL = 15 pF	4
Propagation delay A→Y	tP, A→Y		6	10	ns	3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, RS = RT = 50 Ω, CL = 50 pF	3
Rise time A→Y	tR, A→Y		2	3.5	ns	3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, CL = 50 pF	3
Fall time A→Y	tF, A→Y		2	3.5	ns	3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, CL = 50 pF	3
Channel-to-channel skew A→Y	tSKEW, A→Y		2	4	ns	3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, CL = 50 pF	3
Part-to-part skew A→Y	tPPSKEW, A→Y			3	ns	3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, CL = 50 pF	3
Propagation delay Y→A	tP, Y→A		4	7	ns	3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, RS = RT = 50 Ω, CL = 15 pF	3
Rise time Y→A	tR, Y→A		1	3	ns	3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, CL = 15 pF	3
Fall time Y→A	tF, Y→A		3	7	ns	3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, CL = 15 pF	3
Channel-to-channel skew Y→A	tSKEW, Y→A		2	3.5	ns	3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, CL = 15 pF	3
Part-to-part skew Y→A	tPPSKEW, Y→A			2	ns	3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, CL = 15 pF	3
Propagation delay A→Y	tP, A→Y		8	11	ns	1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, RS = RT = 50 Ω, CL = 50 pF	4
Rise time A→Y	tR, A→Y		2	5	ns	1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, CL = 50 pF	4
Fall time A→Y	tF, A→Y		2	5	ns	1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, CL = 50 pF	4
Channel-to-channel skew A→Y	tSKEW, A→Y		2	4	ns	1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, CL = 50 pF	4
Part-to-part skew A→Y	tPPSKEW, A→Y			4	ns	1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, CL = 50 pF	4
Propagation delay Y→A	tP, Y→A		5	8	ns	1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, RS = RT = 50 Ω, CL = 15 pF	4
Rise time Y→A	tR, Y→A		2	3.5	ns	1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, CL = 15 pF	4
Fall time Y→A	tF, Y→A		2	3.5	ns	1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, CL = 15 pF	4
Channel-to-channel skew Y→A	tSKEW, Y→A		2	3	ns	1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, CL = 15 pF	4
Part-to-part skew Y→A	tPPSKEW, Y→A			3	ns	1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, CL = 15 pF	4
VCCA to GND	VCCA	-0.3		7	V	TA = 25°C	6
VCCY to GND	VCCY			7	V	TA = 25°C; lower limit printed as VCCA	6
EN to GND	EN	-0.3		7	V	TA = 25°C	6
Operating temperature range (B Version)		-40		85	°C	Extended Industrial Range	6
Storage temperature range		-65		150	°C		6
Junction temperature	TJ			150	°C		6
Thermal impedance 20-ball WLCSP	θJA		100		°C/W	20-Ball WLCSP	6
Lead temperature, soldering				300	°C	10 sec	6
IR reflow peak temperature				260	°C	<20 sec, 260°C (+0°C/−5°C)	6

CAD (KiCad official)

Symbol: ADG3308BCBZ-1-RL7
Footprint: Package_CSP:WLCSP-20_1.934x2.434mm_Layout4x5_P0.4mm
3D model: WLCSP-20(2x2.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.35 mm nominal DSBGA height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: adg3308bcbz-1-rl7-etched.step / adg3308bcbz-1-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adg3308bcbz-1-rl7.step / adg3308bcbz-1-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (20 pp, sha256 ec524bb8f7ee3358, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ADG3308BCBZ-1-RL7

Verified ADG3308BCBZ-1-RL7

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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