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CLVC244AQPWRG4Q1

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Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicclvc244aqpwrg4q1factory-2.0.0extractor-text

Verified CLVC244AQPWRG4Q1

by Ray · last 10 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

10 Nov 2026RayPublished by the parts factory: tier mfr, 20 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CLVC244AQPWRG4Q1 · TSSOP-20 · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 34-page datasheet
  • ✓distributor: lcsc C2676047, digikey 296-23657-2-ND, mouser 595-CLVC244AQPWRG4Q1
  • ✓family: TSSOP-20_4.4x6.5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-dsxv5iwf/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.28)
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 34 kB, viewers/symbol.html 16 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ clvc244aqpwrg4q1.kicad_sym✓ clvc244aqpwrg4q1.kicad_mod✓ clvc244aqpwrg4q1.step
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Contents

README

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CLVC244AQPWRG4Q1

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

CLVC244AQPWRG4Q1 from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-low output enable for bank 1: when low, all 1Yn outputs are enabled; when high, they are disabled and placed in high impedance.
2 1A1 input Data input for port 1A1 of bank 1; the datasheet limits input voltage to 0 V to 5.5 V.
3 2Y4 output Balanced CMOS three-state output of port 2Y4 of bank 2; continuous output current is limited to ±50 mA.
4 1A2 input Data input for port 1A2 of bank 1; the datasheet limits input voltage to 0 V to 5.5 V.
5 2Y3 output Balanced CMOS three-state output of port 2Y3 of bank 2; continuous output current is limited to ±50 mA.
6 1A3 input Data input for port 1A3 of bank 1; the datasheet limits input voltage to 0 V to 5.5 V.
7 2Y2 output Balanced CMOS three-state output of port 2Y2 of bank 2; continuous output current is limited to ±50 mA.
8 1A4 input Data input for port 1A4 of bank 1; the datasheet limits input voltage to 0 V to 5.5 V.
9 2Y1 output Balanced CMOS three-state output of port 2Y1 of bank 2; continuous output current is limited to ±50 mA.
10 GND power_in Ground reference pin.
11 2A1 input Data input for port 2A1 of bank 2; the datasheet limits input voltage to 0 V to 5.5 V.
12 1Y4 output Balanced CMOS three-state output of port 1Y4 of bank 1; continuous output current is limited to ±50 mA.
13 2A2 input Data input for port 2A2 of bank 2; the datasheet limits input voltage to 0 V to 5.5 V.
14 1Y3 output Balanced CMOS three-state output of port 1Y3 of bank 1; continuous output current is limited to ±50 mA.
15 2A3 input Data input for port 2A3 of bank 2; the datasheet limits input voltage to 0 V to 5.5 V.
16 1Y2 output Balanced CMOS three-state output of port 1Y2 of bank 1; continuous output current is limited to ±50 mA.
17 2A4 input Data input for port 2A4 of bank 2; the datasheet limits input voltage to 0 V to 5.5 V.
18 1Y1 output Balanced CMOS three-state output of port 1Y1 of bank 1; continuous output current is limited to ±50 mA.
19 2OE input Active-low output enable for bank 2: when low, all 2Yn outputs are enabled; when high, they are disabled and placed in high impedance.
20 VCC power_in Supply pin; operating range is 1.65 V to 3.6 V, and a 0.1 µF bypass capacitor is recommended close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 6.5 V 5
Input voltage VI -0.5 6.5 V 5
Voltage applied to any output in high-impedance or power-off state VO -0.5 6.5 V 5
Voltage applied to any output in high or low state VO -0.5 V Max printed as VCC + 0.5 V; not converted 5
Input clamp current IIK -50 mA VI < 0 5
Output clamp current IOK -50 mA VO < 0 5
Continuous output current IO -50 50 mA 5
Continuous current through VCC or GND -100 100 mA 5
Power dissipation Ptot 500 mW TA = -40°C to +125°C 5
Junction temperature TJ 150 °C 5
Storage temperature Tstg -65 150 °C 5
Supply voltage, operating VCC 1.65 3.6 V Operating 6
Supply voltage, data retention only VCC 1.5 V Data retention only 6
High-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 6
High-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 6
Low-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 6
Low-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 6
Input voltage VI 0 5.5 V 6
Output voltage VO 0 V Max printed as VCC; not converted 6
High-level output current IOH -4 mA VCC = 1.65 V 6
High-level output current IOH -8 mA VCC = 2.3 V 6
High-level output current IOH -12 mA VCC = 2.7 V 6
High-level output current IOH -24 mA VCC = 3 V 6
Low-level output current IOL 4 mA VCC = 1.65 V 6
Low-level output current IOL 8 mA VCC = 2.3 V 6
Low-level output current IOL 12 mA VCC = 2.7 V 6
Low-level output current IOL 24 mA VCC = 3 V 6
Ambient temperature TA -40 125 °C All packages other than BGA (applies to PW) 6
High-level output voltage VOH 1.05 V IOH = -4 mA, VCC = 1.65 V, TA = -40°C to +125°C 7
High-level output voltage VOH 1.55 V IOH = -8 mA, VCC = 2.3 V, TA = -40°C to +125°C 7
High-level output voltage VOH 2.05 V IOH = -12 mA, VCC = 2.7 V, TA = -40°C to +125°C 7
High-level output voltage VOH 2.25 V IOH = -12 mA, VCC = 3 V, TA = -40°C to +125°C 7
High-level output voltage VOH 2 V IOH = -24 mA, VCC = 3 V, TA = -40°C to +125°C 7
Low-level output voltage VOL 0.3 V IOL = 100 µA, VCC = 1.65 V to 3.6 V, TA = -40°C to +125°C 7
Low-level output voltage VOL 0.6 V IOL = 4 mA, VCC = 1.65 V, TA = -40°C to +125°C 7
Low-level output voltage VOL 0.75 V IOL = 8 mA, VCC = 2.3 V, TA = -40°C to +125°C 7
Low-level output voltage VOL 0.8 V IOL = 24 mA, VCC = 3 V, TA = -40°C to +125°C 7
Input leakage current II -20 20 µA VI = 5.5 V or GND, VCC = 3.6 V, TA = -40°C to +125°C 7
Power-off leakage current Ioff -20 20 µA VI or VO = 5.5 V, VCC = 0, TA = -40°C to +125°C 7
High-impedance output leakage current IOZ -20 20 µA VO = 0 to 5.5 V, VCC = 3.6 V, TA = -40°C to +125°C 7
Quiescent supply current ICC 40 µA VI = VCC or GND, IO = 0, VCC = 3.6 V, TA = -40°C to +125°C 7
Additional quiescent supply current per input ΔICC 5000 µA One input at VCC - 0.6 V, other inputs at VCC or GND, VCC = 2.7 V to 3.6 V, TA = -40°C to +125°C 7
Propagation delay A to Y tpd 12.4 ns VCC = 1.8 V ±0.15 V, TA = -40°C to +125°C 8
Propagation delay A to Y tpd 10 ns VCC = 2.5 V ±0.2 V, TA = -40°C to +125°C 8
Propagation delay A to Y tpd 8.2 ns VCC = 2.7 V, TA = -40°C to +125°C 8
Propagation delay A to Y tpd 7.2 ns VCC = 3.3 V ±0.3 V, TA = -40°C to +125°C 8
Enable time OE to Y ten 14.1 ns VCC = 1.8 V ±0.15 V, TA = -40°C to +125°C 8
Enable time OE to Y ten 11.7 ns VCC = 2.5 V ±0.2 V, TA = -40°C to +125°C 8
Enable time OE to Y ten 10.3 ns VCC = 2.7 V, TA = -40°C to +125°C 8
Enable time OE to Y ten 9.4 ns VCC = 3.3 V ±0.3 V, TA = -40°C to +125°C 8
Disable time OE to Y tdis 13.6 ns VCC = 1.8 V ±0.15 V, TA = -40°C to +125°C 8
Disable time OE to Y tdis 9.9 ns VCC = 2.5 V ±0.2 V, TA = -40°C to +125°C 8
Disable time OE to Y tdis 8.6 ns VCC = 2.7 V, TA = -40°C to +125°C 8
Disable time OE to Y tdis 8 ns VCC = 3.3 V ±0.3 V, TA = -40°C to +125°C 8
Output skew tsk(o) 1 1.5 ns VCC = 3.3 V ±0.3 V 8
Thermal resistance, junction-to-ambient (PW package) RθJA 83 °C/W PW (TSSOP) package, JESD 51-7 6

CAD (KiCad official)

  • Symbol: CLVC244AQPWRG4Q1
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: clvc244aqpwrg4q1-etched.step / clvc244aqpwrg4q1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); clvc244aqpwrg4q1.step / clvc244aqpwrg4q1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 29313fce9f65acd2, retrieved 2026-11-10, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF