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ADS130B04QPWRQ1

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TEXAS INSTRUMENTS Global Sourcing Parts, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ADS130B04QPWRQ1

TEXAS INSTRUMENTS · Global Sourcing Parts · TSSOP-20

ADS130B04QPWRQ1 from TEXAS INSTRUMENTS, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD power_in Analog supply; connect a 1-µF capacitor to AGND (2.7 V to 3.6 V recommended operating range, 3.9 V absolute max).
2 AGND power_in Analog ground.
3 AIN0P input Positive analog input 0.
4 AIN0N input Negative analog input 0.
5 AIN1N input Negative analog input 1.
6 AIN1P input Positive analog input 1.
7 AIN2P input Positive analog input 2.
8 AIN2N input Negative analog input 2.
9 AIN3N input Negative analog input 3.
10 AIN3P input Positive analog input 3.
11 SYNC/RESET input Conversion synchronization or system reset; active low.
12 CS input Chip select; active low.
13 DRDY output Data ready; active low.
14 SCLK input Serial data clock.
15 DOUT output Serial data output.
16 DIN input Serial data input.
17 CLKIN input External clock input; tie to DGND if the internal oscillator is used.
18 CAP power_out Digital low-dropout (LDO) regulator output; connect a 220-nF capacitor to DGND.
19 DGND power_in Digital ground.
20 DVDD power_in Digital I/O supply; connect a 1-µF capacitor to DGND (2.7 V to 3.6 V recommended operating range, 3.9 V absolute max).

Key specifications

Parameter Value
Manufacturer TEXAS INSTRUMENTS
Package TSSOP-20
Category Global Sourcing Parts
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog power supply AVDD to AGND AVDD 2.7 3.3 3.6 V 5
AGND to DGND -0.3 0 0.3 V 5
Digital power supply DVDD to DGND DVDD 2.7 3.3 3.6 V 5
External clock frequency, high-resolution mode fCLKIN 0.3 8.192 8.2 MHz High-resolution mode 5
External clock frequency, low-power mode fCLKIN 0.3 4.096 4.15 MHz Low-power mode 5
External clock frequency, very-low-power mode fCLKIN 0.3 2.048 2.08 MHz Very-low-power mode 5
External clock duty cycle 40 50 60 % 5
Operating ambient temperature TA -40 125 °C 5
AVDD to AGND -0.3 3.9 V 4
AGND to DGND -0.3 0.3 V 4
DVDD to DGND -0.3 3.9 V 4
CAP to DGND -0.3 2.2 V 4
Input current -10 10 mA Continuous, all pins except power-supply pins 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -60 150 °C 4
ESD HBM V(ESD) -2000 2000 V Human-body model, per AEC Q100-002 4
ESD CDM corner pins V(ESD) -750 750 V Charged-device model, corner pins 4
ESD CDM other pins V(ESD) -500 500 V Charged-device model, all other non-corner pins 4
Junction-to-ambient thermal resistance RθJA 91.5 °C/W PW (TSSOP), 20 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 31.4 °C/W PW (TSSOP), 20 pins 5
Junction-to-board thermal resistance RθJB 43 °C/W PW (TSSOP), 20 pins 5
Absolute input current, global-chop disabled -1 1 nA Global-chop disabled, VAINxP = VAINxN = 0 V 6
Absolute input current, global-chop enabled -1 1 nA Global-chop enabled, VAINxP = VAINxN = 0 V 6
Differential input current, global-chop disabled -50 50 pA Global-chop disabled, VAINxP = VAINxN = 0 V 6
Differential input current, global-chop enabled -30 30 pA Global-chop enabled, VAINxP = VAINxN = 0 V 6
Offset error, global-chop disabled -800 200 800 µV Global-chop disabled; typ printed ±200 6
Offset error, global-chop enabled -4 0.4 4 µV Global-chop enabled; typ printed ±0.4 6
Offset drift, gain 1 to 4 100 500 nV/°C Global-chop disabled, gain = 1 to 4 6
Offset drift, gain 8 to 128 50 200 nV/°C Global-chop disabled, gain = 8 to 128 6
Offset drift, global-chop enabled 10 30 nV/°C Global-chop enabled 6
Gain error -0.7 0.2 0.7 % Including error of internal voltage reference, TA = 25°C; typ printed ±0.2% 6
Gain drift, gain 1 to 4 8 30 ppm/°C Including drift of internal voltage reference, TA = -40°C to +85°C, gain = 1 to 4 6
Gain drift, gain 8 to 128 7 25 ppm/°C Including drift of internal voltage reference, TA = -40°C to +85°C, gain = 8 to 128 6
Gain drift, full temperature 13 40 ppm/°C Including drift of internal voltage reference, TA = -40°C to +125°C 6
Internal oscillator accuracy fOSC -5 0.5 2.5 % typ printed ±0.5% 7
Input current, digital inputs IIN -1 1 µA DGND < VDigital Input < DVDD 7
Analog supply current, HR mode, gain 1, 2 IAVDD 5.6 6.8 mA High-resolution mode, gain = 1, 2 7
Analog supply current, HR mode, gain 4 to 128 IAVDD 6.4 8 mA High-resolution mode, gain = 4 to 128 7
Analog supply current, LP mode, gain 1, 2 IAVDD 2.8 3.4 mA Low-power mode, gain = 1, 2 7
Analog supply current, VLP mode, gain 1, 2 IAVDD 1.4 2 mA Very-low-power mode, gain = 1, 2 7
Digital supply current, HR mode IDVDD 0.4 0.5 mA High-resolution mode 7
Digital supply current, LP mode IDVDD 0.2 0.3 mA Low-power mode 7
Digital supply current, VLP mode IDVDD 0.1 0.2 mA Very-low-power mode 7
Power dissipation, HR mode, gain 1, 2 PD 19.8 24.1 mW High-resolution mode, gain = 1, 2 7
Power dissipation, HR mode, gain 4 to 128 PD 22.4 28.1 mW High-resolution mode, gain = 4 to 128 7
Differential input impedance, global-chop disabled Zin 25 MΩ Global-chop disabled 6
Differential input impedance, global-chop enabled Zin 300 MΩ Global-chop enabled 6
Internal reference voltage VREF 1.2 V 7
Crosstalk -120 dB fIN = 50 Hz or 60 Hz 7
SCLK period tc(SC) 40 ns 2.7 V ≤ DVDD ≤ 3.6 V 8
Delay time, first SCLK rising edge after CS falling edge td(CSSC) 16 ns 2.7 V ≤ DVDD ≤ 3.6 V 8
Setup time, DIN valid before SCLK falling edge tsu(DI) 5 ns 2.7 V ≤ DVDD ≤ 3.6 V 8
Propagation delay, SCLK rising edge to valid new DOUT tp(SCDO) 20 ns 2.7 V ≤ DVDD ≤ 3.6 V, DOUT load = 20 pF // 100 kΩ 8
Power-on-reset time tPOR 250 µs Measured from supplies at 90% to first DRDY rising edge 8

CAD (KiCad official)

  • Symbol: ADS130B04QPWRQ1
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: ads130b04qpwrq1-etched.step / ads130b04qpwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads130b04qpwrq1.step / ads130b04qpwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TEXAS INSTRUMENTS datasheet (61 pp, sha256 95e3b89062ede92c, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF