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FT2232D-REEL

Public Made by Adom

by adom

FTDI USB Converters, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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FT2232D-REEL

FTDI · USB Converters · LQFP-48(7x7)

FT2232D-REEL from FTDI, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EESK output Clock output to the external EEPROM, tri-stated during device reset and driven out otherwise.
2 EEDATA bidirectional EEPROM data I/O, connected directly to EEPROM Data-In and to EEPROM Data-Out via a 2.2K resistor, with Data-Out pulled to VCC by a 10K resistor; tri-stated during device reset.
3 VCC power_in Supply to the device core, LDO and non-UART/FIFO interface pins, +4.35 V to +5.25 V.
4 RESET# input External reset input for the FT2232D; tie to VCC if not used.
5 RSTOUT# output Output of the internal reset generator, driven low for 5.6 ms after VCC > 3.5 V and clock start-up, then clamped to the 3.3 V LDO output, forced low by RESET#, and not affected by a USB bus reset.
6 3V3OUT power_out 3.3 V output of the integrated LDO regulator, to be decoupled to GND with 33nF, supplying the USB transceiver and RSTOUT# and sourcing at most 5 mA for external 3.3 V logic.
7 USBDP bidirectional USB Data Signal Plus, requiring a 1.5K pull-up to 3V3OUT or RSTOUT#.
8 USBDM bidirectional USB Data Signal Minus.
9 GND power_in Device ground supply pin.
10 SI/WUA bidirectional Channel A SI/WU pin used for USB suspend and resume support, and not available in the MCU host bus, CPU FIFO and fast opto-isolated modes.
11 ACBUS3 bidirectional Channel A control bus bit 3, which is TXLED# (transmit LED drive) in 232 UART mode and WR in 245 FIFO mode, with other functions in other modes.
12 ACBUS2 bidirectional Channel A control bus bit 2, which is RXLED# (receive LED drive) in 232 UART mode and RD# in 245 FIFO mode, with other functions in other modes.
13 ACBUS1 bidirectional Channel A control bus bit 1, which is SLEEP# in 232 UART mode and TXE# in 245 FIFO mode, with other functions in other modes.
14 VCCIOA power_in Supply for the channel A UART/FIFO interface pins, +3.0 V to +5.25 V, connected to a 3.3 V supply for 3.3 V logic or to VCC for 5 V CMOS output levels.
15 ACBUS0 bidirectional Channel A control bus bit 0, which is TXDEN (RS485 transmit enable) in 232 UART mode and RXF# in 245 FIFO mode, with other functions in other modes.
16 ADBUS7 bidirectional Channel A data bus bit 7, which is RI# in 232 UART mode and D7 in 245 FIFO mode.
17 ADBUS6 bidirectional Channel A data bus bit 6, which is DCD# in 232 UART mode and D6 in 245 FIFO mode.
18 GND power_in Device ground supply pin.
19 ADBUS5 bidirectional Channel A data bus bit 5, which is DSR# in 232 UART mode and D5 in 245 FIFO mode.
20 ADBUS4 bidirectional Channel A data bus bit 4, which is DTR# in 232 UART mode and D4 in 245 FIFO mode.
21 ADBUS3 bidirectional Channel A data bus bit 3, which is CTS# in 232 UART mode and D3 in 245 FIFO mode.
22 ADBUS2 bidirectional Channel A data bus bit 2, which is RTS# in 232 UART mode and D2 in 245 FIFO mode.
23 ADBUS1 bidirectional Channel A data bus bit 1, which is RXD in 232 UART mode and D1 in 245 FIFO mode.
24 ADBUS0 bidirectional Channel A data bus bit 0, which is TXD in 232 UART mode and D0 in 245 FIFO mode.
25 GND power_in Device ground supply pin.
26 SI/WUB bidirectional Channel B SI/WU pin used for USB suspend and resume support, and not available in the MCU host bus, MPSSE and CPU FIFO modes.
27 BCBUS3 bidirectional Channel B control bus bit 3, which is TXLED# (transmit LED drive) in 232 UART mode and WR in 245 FIFO mode, with other functions in other modes.
28 BCBUS2 bidirectional Channel B control bus bit 2, which is RXLED# (receive LED drive) in 232 UART mode and RD# in 245 FIFO mode, with other functions in other modes.
29 BCBUS1 bidirectional Channel B control bus bit 1, which is SLEEP# in 232 UART mode and TXE# in 245 FIFO mode, with other functions in other modes.
30 BCBUS0 bidirectional Channel B control bus bit 0, which is TXDEN (RS485 transmit enable) in 232 UART mode and RXF# in 245 FIFO mode, with other functions in other modes.
31 VCCIOB power_in Supply for the channel B UART/FIFO interface pins, +3.0 V to +5.25 V, connected to a 3.3 V supply for 3.3 V logic or to VCC for 5 V CMOS output levels.
32 BDBUS7 bidirectional Channel B data bus bit 7, which is RI# in 232 UART mode and D7 in 245 FIFO mode.
33 BDBUS6 bidirectional Channel B data bus bit 6, which is DCD# in 232 UART mode and D6 in 245 FIFO mode.
34 GND power_in Device ground supply pin.
35 BDBUS5 bidirectional Channel B data bus bit 5, which is DSR# in 232 UART mode and D5 in 245 FIFO mode.
36 BDBUS4 bidirectional Channel B data bus bit 4, which is DTR# in 232 UART mode and D4 in 245 FIFO mode.
37 BDBUS3 bidirectional Channel B data bus bit 3, which is CTS# in 232 UART mode and D3 in 245 FIFO mode.
38 BDBUS2 bidirectional Channel B data bus bit 2, which is RTS# in 232 UART mode and D2 in 245 FIFO mode.
39 BDBUS1 bidirectional Channel B data bus bit 1, which is RXD in 232 UART mode and D1 in 245 FIFO mode.
40 BDBUS0 bidirectional Channel B data bus bit 0, which is TXD in 232 UART mode and D0 in 245 FIFO mode.
41 PWREN# output Goes low after USB configuration and high during USB suspend, usable to switch external logic power through a P-channel logic-level MOSFET when the EEPROM interface pull-down option is enabled.
42 VCC power_in Supply to the device core, LDO and non-UART/FIFO interface pins, +4.35 V to +5.25 V.
43 XTIN input Input to the 6 MHz crystal oscillator, which can also be driven by a 5 V CMOS clock or an AC-coupled clock centred on VCC/2.
44 XTOUT output Output of the 6 MHz crystal oscillator, which stops oscillating during USB suspend.
45 AGND power_in Analog ground supply for the internal x8 clock multiplier.
46 AVCC power_in Analog supply for the internal x8 clock multiplier, filtered by a 470 Ohm series resistor and 100 nF to GND.
47 TEST input IC test mode input that must be tied to GND for normal operation.
48 EECS bidirectional EEPROM chip select, tri-stated during device reset and connected to the EEPROM CS pin.

Key specifications

Parameter Value
Manufacturer FTDI
Package LQFP-48(7x7)
Category Interface
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC Operating Supply Voltage Vcc1 4.35 5 5.25 V 18
VCCIO Operating Supply Voltage Vcc2 3 5.25 V 18
Operating Supply Current (USB Suspend) Icc2 100 200 μA USB Suspend 18
Output Voltage High (IO pins, standard drive) Voh 3.2 4.1 4.9 V VCCIO = 5.0V, Standard Drive Level; I source = 2mA 18
Output Voltage Low (IO pins, standard drive) Vol 0.3 0.4 0.6 V VCCIO = 5.0V, Standard Drive Level; I sink = 2mA 18
Input Switching Threshold (IO pins, standard drive) Vin 1.3 1.6 1.9 V VCCIO = 5.0V, Standard Drive Level 18
Input Switching Hysteresis (IO pins, standard drive) VHys 50 55 60 mV VCCIO = 5.0V, Standard Drive Level 18
Output Voltage High (IO pins, standard drive) Voh 2.2 2.7 3.2 V VCCIO = 3.0 - 3.6V, Standard Drive Level; I source = 1 mA 18
Output Voltage Low (IO pins, standard drive) Vol 0.3 0.4 0.5 V VCCIO = 3.0 - 3.6V, Standard Drive Level; I sink = 2 mA 18
Input Switching Threshold (IO pins, standard drive) Vin 1 1.2 1.5 V VCCIO = 3.0 - 3.6V, Standard Drive Level 18
Input Switching Hysteresis (IO pins, standard drive) VHys 20 25 30 mV VCCIO = 3.0 - 3.6V, Standard Drive Level 18
Output Voltage High (IO pins, high drive) Voh 3.2 4.1 4.9 V VCCIO = 5.0V, High Drive Level; I source = 6 mA 18
Output Voltage Low (IO pins, high drive) Vol 0.3 0.4 0.6 V VCCIO = 5.0V, High Drive Level; I sink = 6 mA 18
Input Switching Threshold (IO pins, high drive) Vin 1.3 1.6 1.9 V VCCIO = 5.0V, High Drive Level 18
Input Switching Hysteresis (IO pins, high drive) VHys 50 55 60 mV VCCIO = 5.0V, High Drive Level 18
Output Voltage High (IO pins, high drive) Voh 2.2 2.8 3.2 V VCCIO = 3.0 - 3.6V, High Drive Level; I source = 3mA 18
Input Switching Threshold (IO pins, high drive) Vin 1 1.2 1.5 V VCCIO = 3.0 - 3.6V, High Drive Level 18
Input Switching Hysteresis (IO pins, high drive) VHys 20 25 30 mV VCCIO = 3.0 - 3.6V, High Drive Level 18
Output Voltage High (XTIN/XTOUT) Voh 4 5 V Fosc = 6MHz 19
Output Voltage Low (XTIN/XTOUT) Vol 0.1 1 V Fosc = 6MHz 19
Input Switching Threshold (XTIN/XTOUT) Vin 1.8 2.5 3.2 V 19
Output Voltage High (RESET#, TEST, EECS, EESK, EEDATA) Voh 3.2 4.1 4.9 V I source = 2mA 19
Output Voltage Low (RESET#, TEST, EECS, EESK, EEDATA) Vol 0.3 0.4 0.6 V I sink = 2 mA 19
Input Switching Threshold (RESET#, TEST, EECS, EESK, EEDATA) Vin 1.3 1.6 1.9 V 19
Input Switching Hysteresis (RESET#, TEST, EECS, EESK, EEDATA) VHys 50 55 60 mV 19
Output Voltage High (RSTOUT#) Voh 3 3.6 V I source = 2mA 19
Output Voltage Low (RSTOUT#) Vol 0.3 0.6 V I sink = 2mA 19
USB IO Pins Static Output (High) UVoh 2.8 3.6 V RI = 1.5K to 3V3Out (D+); RI = 15K to GND (D-) 19
USB IO Pins Static Output (Low) UVol 0 0.3 V RI = 1.5K to 3V3Out (D+); RI = 15K to GND (D-) 19
Single Ended Rx Threshold UVse 0.8 2 V 19
Differential Common Mode UCom 0.8 2.5 V 19
Differential Input Sensitivity UVDif 0.2 V 19
Driver Output Impedance UDrvZ 29 44 Ohm Includes external 27R series resistors on USBDP and USBDM (Note 15) 19
Storage Temperature -65 150 °C 17
Ambient Temperature (Power Applied) -40 85 °C 17
VCC Supply Voltage VCC -0.5 6 V 17
DC Input Voltage - Inputs -0.5 V Upper limit printed as VCC + 0.5V 17
DC Input Voltage - High Impedance Bidirectionals -0.5 V Upper limit printed as VCC + 0.5V 17
DC Output Current - Outputs 24 mA 17
DC Output Current - Low Impedance Bidirectionals 24 mA 17
Power Dissipation 500 mW VCC = 5.25V 17
Electrostatic Discharge Voltage (Human Body Model) -3000 3000 V I < 1μA 17
Latch Up Current -200 200 mA Vi = +/-10V maximum, for 10 ms 17

CAD (KiCad official)

  • Symbol: FT2232D-REEL
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ft2232d-reel-etched.step / ft2232d-reel-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ft2232d-reel.step / ft2232d-reel.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: FTDI datasheet (56 pp, sha256 673e1ccd2b5d6b77, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF