CD74HC373M96 from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OE	input	Buffered active-low output enable; when high, the eight outputs are placed in the high-impedance state without affecting the latches.
2	1Q	tri_state	Latch 1 output, which follows D when LE is high and holds the latched value when LE is low, and goes high-impedance when OE is high.
3	1D	input	Latch 1 data input, sampled while LE is high and held when LE falls.
4	2D	input	Latch 2 data input, sampled while LE is high and held when LE falls.
5	2Q	tri_state	Latch 2 output, which follows D when LE is high and holds the latched value when LE is low, and goes high-impedance when OE is high.
6	3Q	tri_state	Latch 3 output, which follows D when LE is high and holds the latched value when LE is low, and goes high-impedance when OE is high.
7	3D	input	Latch 3 data input, sampled while LE is high and held when LE falls.
8	4D	input	Latch 4 data input, sampled while LE is high and held when LE falls.
9	4Q	tri_state	Latch 4 output, which follows D when LE is high and holds the latched value when LE is low, and goes high-impedance when OE is high.
10	GND	power_in	Ground reference for the device; all unused inputs must be tied to GND or VCC.
11	LE	input	Latch enable; when high the Q outputs follow the D inputs, and when low the Q outputs are latched.
12	5Q	tri_state	Latch 5 output, which follows D when LE is high and holds the latched value when LE is low, and goes high-impedance when OE is high.
13	5D	input	Latch 5 data input, sampled while LE is high and held when LE falls.
14	6D	input	Latch 6 data input, sampled while LE is high and held when LE falls.
15	6Q	tri_state	Latch 6 output, which follows D when LE is high and holds the latched value when LE is low, and goes high-impedance when OE is high.
16	7Q	tri_state	Latch 7 output, which follows D when LE is high and holds the latched value when LE is low, and goes high-impedance when OE is high.
17	7D	input	Latch 7 data input, sampled while LE is high and held when LE falls.
18	8D	input	Latch 8 data input, sampled while LE is high and held when LE falls.
19	8Q	tri_state	Latch 8 output, which follows D when LE is high and holds the latched value when LE is low, and goes high-impedance when OE is high.
20	VCC	power_in	Positive supply, specified for 2 V to 6 V operation; each VCC terminal should have a bypass capacitor, 0.1 µF recommended.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-20-300mil
Category	Logic
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage range	VCC	-0.5		7	V	Over operating free-air temperature range	4
Input clamp current	IIK	-20		20	mA	VI < 0 or VI > VCC	4
Output clamp current	IOK	-20		20	mA	VO < 0 or VO > VCC	4
Continuous output drain current per output	IO	-35		35	mA	VO = 0 to VCC	4
Continuous output source or sink current per output	IO	-25		25	mA	VO = 0 to VCC	4
Continuous current through VCC or GND		-50		50	mA		4
Junction temperature	TJ			150	°C		4
Storage temperature range	Tstg	-65		150	°C		4
Supply voltage	VCC	2		6	V		4
High-level input voltage	VIH	1.5			V	VCC = 2 V	4
High-level input voltage	VIH	3.15			V	VCC = 4.5 V	4
High-level input voltage	VIH	4.2			V	VCC = 6 V	4
Low-level input voltage	VIL			0.5	V	VCC = 2 V	4
Low-level input voltage	VIL			1.35	V	VCC = 4.5 V	4
Low-level input voltage	VIL			1.8	V	VCC = 6 V	4
Input voltage	VI	0			V	Upper limit is VCC	4
Output voltage	VO	0			V	Upper limit is VCC	4
Input transition (rise and fall) time	tt			1000	ns	VCC = 2 V	4
Input transition (rise and fall) time	tt			500	ns	VCC = 4.5 V	4
Input transition (rise and fall) time	tt			400	ns	VCC = 6 V	4
Operating free-air temperature	TA	-55		125	°C		4
High-level output voltage	VOH	1.9			V	VI = VIH or VIL, IOH = -20 µA, VCC = 2 V, TA = 25°C	5
High-level output voltage	VOH	4.4			V	VI = VIH or VIL, IOH = -20 µA, VCC = 4.5 V, TA = 25°C	5
High-level output voltage	VOH	5.9			V	VI = VIH or VIL, IOH = -20 µA, VCC = 6 V, TA = 25°C	5
High-level output voltage	VOH	3.98			V	VI = VIH or VIL, IOH = -6 mA, VCC = 4.5 V, TA = 25°C	5
High-level output voltage	VOH	3.7			V	VI = VIH or VIL, IOH = -6 mA, VCC = 4.5 V, TA = -55°C to 125°C	5
High-level output voltage	VOH	5.48			V	VI = VIH or VIL, IOH = -7.8 mA, VCC = 6 V, TA = 25°C	5
High-level output voltage	VOH	5.2			V	VI = VIH or VIL, IOH = -7.8 mA, VCC = 6 V, TA = -55°C to 125°C	5
Low-level output voltage	VOL			0.1	V	VI = VIH or VIL, IOL = 20 µA, VCC = 2 V, TA = 25°C	5
Low-level output voltage	VOL			0.26	V	VI = VIH or VIL, IOL = 6 mA, VCC = 4.5 V, TA = 25°C	5
Low-level output voltage	VOL			0.4	V	VI = VIH or VIL, IOL = 6 mA, VCC = 4.5 V, TA = -55°C to 125°C	5
Input leakage current	II	-0.1		0.1	µA	VI = VCC or 0, VCC = 6 V, TA = 25°C	5
Input leakage current	II	-1		1	µA	VI = VCC or 0, VCC = 6 V, TA = -55°C to 125°C	5
Off-state output leakage current	IOZ	-0.5		0.5	µA	VO = VCC or 0, VCC = 6 V, TA = 25°C	5
Off-state output leakage current	IOZ	-10		10	µA	VO = VCC or 0, VCC = 6 V, TA = -55°C to 125°C	5
Quiescent supply current	ICC			8	µA	VI = VCC or 0, IO = 0, VCC = 6 V, TA = 25°C	5
Quiescent supply current	ICC			160	µA	VI = VCC or 0, IO = 0, VCC = 6 V, TA = -55°C to 125°C	5
Input capacitance	Ci		10		pF		5
Output capacitance	Co		20		pF		5
Junction-to-ambient thermal resistance (DW SOIC)	RθJA		109.1		°C/W		4
Junction-to-case (top) thermal resistance (DW SOIC)	RθJC(top)		76		°C/W		4
Junction-to-board thermal resistance (DW SOIC)	RθJB		77.6		°C/W		4

CAD (KiCad official)

Symbol: CD74HC373M96
Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
3D model: SOIC-20-300mil (KiCad packages3D, STEP)
3D model files: cd74hc373m96-etched.step / cd74hc373m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc373m96.step / cd74hc373m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (21 pp, sha256 c1a1a69ac5b95454, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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CD74HC373M96

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3D Model

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