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ATMEGA32A-MU
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), VQFN-44(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownATMEGA32A-MU
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · VQFN-44(7x7)
ATMEGA32A-MU from Microchip Tech, in a VQFN-44(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PB5 | bidirectional | Port B bit 5 bi-directional I/O with internal pull-up; alternate function MOSI (SPI master data out / slave data in). |
| 2 | PB6 | bidirectional | Port B bit 6 bi-directional I/O with internal pull-up; alternate function MISO (SPI master data in / slave data out). |
| 3 | PB7 | bidirectional | Port B bit 7 bi-directional I/O with internal pull-up; alternate function SCK (SPI bus serial clock). |
| 4 | RESET | input | Active-low reset input; a low level longer than the minimum pulse length generates a reset even if the clock is not running. |
| 5 | VCC | power_in | Digital supply voltage. |
| 6 | GND | power_in | Ground. |
| 7 | XTAL2 | output | Output from the inverting oscillator amplifier. |
| 8 | XTAL1 | input | Input to the inverting oscillator amplifier and to the internal clock operating circuit. |
| 9 | PD0 | bidirectional | Port D bit 0 bi-directional I/O with internal pull-up; alternate function RXD (USART input). |
| 10 | PD1 | bidirectional | Port D bit 1 bi-directional I/O with internal pull-up; alternate function TXD (USART output). |
| 11 | PD2 | bidirectional | Port D bit 2 bi-directional I/O with internal pull-up; alternate function INT0 (external interrupt 0 input). |
| 12 | PD3 | bidirectional | Port D bit 3 bi-directional I/O with internal pull-up; alternate function INT1 (external interrupt 1 input). |
| 13 | PD4 | bidirectional | Port D bit 4 bi-directional I/O with internal pull-up; alternate function OC1B (Timer/Counter1 output compare B). |
| 14 | PD5 | bidirectional | Port D bit 5 bi-directional I/O with internal pull-up; alternate function OC1A (Timer/Counter1 output compare A). |
| 15 | PD6 | bidirectional | Port D bit 6 bi-directional I/O with internal pull-up; alternate function ICP1 (Timer/Counter1 input capture). |
| 16 | PD7 | bidirectional | Port D bit 7 bi-directional I/O with internal pull-up; alternate function OC2 (Timer/Counter2 output compare). |
| 17 | VCC | power_in | Digital supply voltage. |
| 18 | GND | power_in | Ground. |
| 19 | PC0 | bidirectional | Port C bit 0 bi-directional I/O with internal pull-up; alternate function SCL (two-wire serial interface clock). |
| 20 | PC1 | bidirectional | Port C bit 1 bi-directional I/O with internal pull-up; alternate function SDA (two-wire serial interface data). |
| 21 | PC2 | bidirectional | Port C bit 2 bi-directional I/O with internal pull-up; alternate function TCK (JTAG test clock), pull-up active during reset when JTAG is enabled. |
| 22 | PC3 | bidirectional | Port C bit 3 bi-directional I/O with internal pull-up; alternate function TMS (JTAG test mode select), pull-up active during reset when JTAG is enabled. |
| 23 | PC4 | bidirectional | Port C bit 4 bi-directional I/O with internal pull-up; alternate function TDO (JTAG test data out), tri-stated unless TAP states shift out data. |
| 24 | PC5 | bidirectional | Port C bit 5 bi-directional I/O with internal pull-up; alternate function TDI (JTAG test data in), pull-up active during reset when JTAG is enabled. |
| 25 | PC6 | bidirectional | Port C bit 6 bi-directional I/O with internal pull-up; alternate function TOSC1 (Timer oscillator input, used when AS2 is set). |
| 26 | PC7 | bidirectional | Port C bit 7 bi-directional I/O with internal pull-up; alternate function TOSC2 (Timer oscillator output, used when AS2 is set). |
| 27 | AVCC | power_in | Supply voltage for Port A and the A/D converter; must be connected to VCC even if the ADC is unused, through a low-pass filter if the ADC is used. |
| 28 | GND | power_in | Ground. |
| 29 | AREF | input | Analog reference pin for the A/D converter. |
| 30 | PA7 | bidirectional | Port A bit 7 bi-directional I/O with internal pull-up; alternate function ADC7 (ADC input channel 7). |
| 31 | PA6 | bidirectional | Port A bit 6 bi-directional I/O with internal pull-up; alternate function ADC6 (ADC input channel 6). |
| 32 | PA5 | bidirectional | Port A bit 5 bi-directional I/O with internal pull-up; alternate function ADC5 (ADC input channel 5). |
| 33 | PA4 | bidirectional | Port A bit 4 bi-directional I/O with internal pull-up; alternate function ADC4 (ADC input channel 4). |
| 34 | PA3 | bidirectional | Port A bit 3 bi-directional I/O with internal pull-up; alternate function ADC3 (ADC input channel 3). |
| 35 | PA2 | bidirectional | Port A bit 2 bi-directional I/O with internal pull-up; alternate function ADC2 (ADC input channel 2). |
| 36 | PA1 | bidirectional | Port A bit 1 bi-directional I/O with internal pull-up; alternate function ADC1 (ADC input channel 1). |
| 37 | PA0 | bidirectional | Port A bit 0 bi-directional I/O with internal pull-up; alternate function ADC0 (ADC input channel 0). |
| 38 | VCC | power_in | Digital supply voltage. |
| 39 | GND | power_in | Ground. |
| 40 | PB0 | bidirectional | Port B bit 0 bi-directional I/O with internal pull-up; alternate functions T0 (Timer/Counter0 external counter input) and XCK (USART external clock). |
| 41 | PB1 | bidirectional | Port B bit 1 bi-directional I/O with internal pull-up; alternate function T1 (Timer/Counter1 external counter input). |
| 42 | PB2 | bidirectional | Port B bit 2 bi-directional I/O with internal pull-up; alternate functions AIN0 (analog comparator positive input) and INT2 (external interrupt 2 input). |
| 43 | PB3 | bidirectional | Port B bit 3 bi-directional I/O with internal pull-up; alternate functions AIN1 (analog comparator negative input) and OC0 (Timer/Counter0 output compare). |
| 44 | PB4 | bidirectional | Port B bit 4 bi-directional I/O with internal pull-up; alternate function SS (SPI slave select input). |
| 45 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | VQFN-44(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 45 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature | -55 | 125 | °C | 286 | |||
| Storage Temperature | -65 | 150 | °C | 286 | |||
| Voltage on any Pin except RESET with respect to Ground | -0.5 | V | upper limit printed as VCC+0.5V | 286 | |||
| Voltage on RESET with respect to Ground | -0.5 | 13 | V | 286 | |||
| Maximum Operating Voltage | 6 | V | 286 | ||||
| DC Current per I/O Pin | 40 | mA | 286 | ||||
| DC Current VCC Pin | 200 | mA | TQFP/MLF package | 286 | |||
| DC Current GND Pin | 400 | mA | TQFP/MLF package | 286 | |||
| Input Low Voltage except XTAL1 and RESET pins | VIL | -0.5 | V | VCC = 4.5 - 5.5 | 286 | ||
| Input Low Voltage XTAL1 pin | VIL1 | -0.5 | V | VCC = 2.7 - 5.5 | 286 | ||
| Input Low Voltage RESET pin | VIL2 | -0.5 | V | VCC = 2.7 - 5.5 | 286 | ||
| Output Low Voltage (Ports A,B,C,D) | VOL | 0.7 | V | IOL = 20 mA, VCC = 5V | 286 | ||
| Output Low Voltage (Ports A,B,C,D) | VOL | 0.5 | V | IOL = 10 mA, VCC = 3V | 286 | ||
| Output High Voltage (Ports A,B,C,D) | VOH | 4.2 | V | IOH = -20 mA, VCC = 5V | 286 | ||
| Output High Voltage (Ports A,B,C,D) | VOH | 2.2 | V | IOH = -10 mA, VCC = 3V | 286 | ||
| Input Leakage Current I/O Pin, pin low | IIL | 1 | µA | VCC = 5.5V, pin low (absolute value) | 286 | ||
| Input Leakage Current I/O Pin, pin high | IIH | 1 | µA | VCC = 5.5V, pin high (absolute value) | 286 | ||
| Reset Pull-up Resistor | RRST | 30 | 60 | 85 | kΩ | 286 | |
| I/O Pin Pull-up Resistor | Rpu | 20 | 50 | kΩ | 286 | ||
| Power Supply Current Active 4MHz | ICC | 2.1 | 5 | mA | VCC = 3V | 287 | |
| Power Supply Current Active 8MHz | ICC | 7.5 | 15 | mA | VCC = 5V | 287 | |
| Power Supply Current Idle 4MHz | ICC | 0.6 | 2.5 | mA | VCC = 3V | 287 | |
| Power Supply Current Idle 8MHz | ICC | 2.8 | 8 | mA | VCC = 5V | 287 | |
| Power-down Mode Supply Current, WDT enabled | ICC | 10 | 20 | µA | VCC = 3V | 287 | |
| Power-down Mode Supply Current, WDT disabled | ICC | 1 | 10 | µA | VCC = 3V | 287 | |
| Analog Comparator Input Offset Voltage | VACIO | 40 | mV | VCC = 5V, Vin = VCC/2 | 287 | ||
| Analog Comparator Input Leakage Current | IACLK | -50 | 50 | nA | VCC = 5V, Vin = VCC/2 | 287 | |
| Analog Comparator Propagation Delay | tACPD | 750 | ns | VCC = 2.7V | 287 | ||
| Analog Comparator Propagation Delay | tACPD | 500 | ns | VCC = 4.0V | 287 | ||
| Oscillator Frequency | 1/tCLCL | 0 | 8 | MHz | VCC = 2.7V to 5.5V | 288 | |
| Oscillator Frequency | 1/tCLCL | 0 | 16 | MHz | VCC = 4.5V to 5.5V | 288 | |
| Clock Period | tCLCL | 125 | ns | VCC = 2.7V to 5.5V | 288 | ||
| Clock Period | tCLCL | 62.5 | ns | VCC = 4.5V to 5.5V | 288 | ||
| High Time | tCHCX | 50 | ns | VCC = 2.7V to 5.5V | 288 | ||
| High Time | tCHCX | 25 | ns | VCC = 4.5V to 5.5V | 288 | ||
| Low Time | tCLCX | 50 | ns | VCC = 2.7V to 5.5V | 288 | ||
| Low Time | tCLCX | 25 | ns | VCC = 4.5V to 5.5V | 288 | ||
| Rise Time | tCLCH | 1.6 | µs | VCC = 2.7V to 5.5V | 288 | ||
| Rise Time | tCLCH | 0.5 | µs | VCC = 4.5V to 5.5V | 288 | ||
| Fall Time | tCHCL | 1.6 | µs | VCC = 2.7V to 5.5V | 288 | ||
| Fall Time | tCHCL | 0.5 | µs | VCC = 4.5V to 5.5V | 288 | ||
| Change in period from one clock cycle to the next | tCLCL | 2 | % | 288 | |||
| Power-on Reset Threshold Voltage (rising) | VPOT | 1.4 | 2.3 | V | 289 | ||
| Power-on Reset Threshold Voltage (falling) | VPOT | 1.3 | 2.3 | V | 289 | ||
| Minimum pulse width on RESET Pin | tRST | 1.5 | µs | 289 | |||
| Brown-out Reset Threshold Voltage | VBOT | 2.5 | 2.7 | 2.9 | V | BODLEVEL = 1 | 289 |
| Brown-out Reset Threshold Voltage | VBOT | 3.6 | 4 | 4.2 | V | BODLEVEL = 0 | 289 |
| Minimum low voltage period for Brown-out Detection | tBOD | 2 | µs | BODLEVEL = 1 | 289 | ||
| Bandgap reference voltage | VBG | 1.15 | 1.23 | 1.35 | V | 289 | |
| Bandgap reference start-up time | tBG | 40 | 70 | µs | 289 | ||
| Input Low-voltage (TWI) | VIL | -0.5 | V | 290 | |||
| Output Low-voltage (TWI) | VOL | 0 | 0.4 | V | 3 mA sink current | 290 | |
| Rise Time for both SDA and SCL | tr | 300 | ns | 290 | |||
| Output Fall Time from VIHmin to VILmax | tof | 250 | ns | 10 pF < Cb < 400 pF | 290 | ||
| Spikes Suppressed by Input Filter | tSP | 0 | 50 | ns | 290 | ||
| Input Current each I/O Pin | Ii | -10 | 10 | µA | 0.1VCC < Vi < 0.9VCC | 290 | |
| Capacitance for each I/O Pin | Ci | 10 | pF | 290 | |||
| SCL Clock Frequency | fSCL | 0 | 400 | kHz | fCK > max(16fSCL, 250kHz) | 290 |
CAD (KiCad official)
- Symbol:
ATMEGA32A-MU - Footprint:
Package_DFN_QFN:QFN-44-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-44(7x7) (KiCad packages3D, STEP)
- 3D model files:
atmega32a-mu-etched.step/atmega32a-mu-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atmega32a-mu.step/atmega32a-mu.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (339 pp, sha256
a12026626ab84321, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).