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A1330LLETR-T
Public Made by Adomby adom
Allegro MicroSystems, LLC Angle, Linear Position Sensors, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownA1330LLETR-T
Allegro MicroSystems, LLC · Angle, Linear Position Sensors · TSSOP-8
A1330LLETR-T from Allegro MicroSystems, LLC, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Device power supply with a 4.5 to 5.5 V operating supply range; it also serves as the Manchester communication input pin. |
| 2 | VOUT | bidirectional | Angle output (analog or PWM), which also carries Manchester output during serial communication and receives EEPROM programming pulses; the forward output voltage is limited to VCC + 2 V (16 V maximum) and the reverse output voltage to 0.5 V. |
| 3 | NC | unconnected | Not connected internally; tie to ground for optimal ESD performance. |
| 4 | GND | power_in | Ground connection for the device, which is also the pin monitored for broken ground wire detection. |
| 5 | NC | unconnected | Not connected internally; tie to ground for optimal ESD performance. |
| 6 | NC | unconnected | Not connected internally; tie to ground for optimal ESD performance. |
| 7 | NC | unconnected | Not connected internally; tie to ground for optimal ESD performance. |
| 8 | NC | unconnected | Not connected internally; tie to ground for optimal ESD performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | TSSOP-8 |
| Category | Sensors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Forward Supply Voltage | VCC | 26.5 | V | Not sampling angles | 2 | ||
| Reverse Supply Voltage | VRCC | -18 | V | Not sampling angles | 2 | ||
| Forward Output Voltage | VOUT | 16 | V | VOUT < VCC + 2 V | 2 | ||
| Reverse Output Voltage | VROUT | 0.5 | V | 2 | |||
| Operating Ambient Temperature | TA | -40 | 150 | °C | L range | 2 | |
| Maximum Junction Temperature | TJ(max) | 165 | °C | 2 | |||
| Storage Temperature | Tstg | -65 | 170 | °C | 2 | ||
| Package Thermal Resistance | RθJA | 145 | °C/W | LE-8 single die package | 2 | ||
| Supply Voltage | VCC | 4.5 | 5.5 | V | 5 | ||
| Supply Current | ICC | 12 | 15 | mA | One die, analog output, unloaded output; TA ≥ 25°C | 5 | |
| Supply Current | ICC | 12.6 | 16 | mA | One die, analog output, unloaded output; TA < 25°C | 5 | |
| Undervoltage Lockout Threshold Voltage (rising) | VUVLO(H) | 4.65 | V | Maximum VCC, dV/dt = 1 V/ms, TA = 25°C, A1330 sampling enabled, rising VCC | 5 | ||
| Undervoltage Lockout Threshold Voltage (falling) | VUVLO(L) | 3.9 | 4.5 | V | Maximum VCC, dV/dt = 1 V/ms, TA = 25°C, A1330 sampling disabled, falling VCC | 5 | |
| Overvoltage Lockout Threshold Voltage (sampling enabled) | VOVLO(L) | 5.5 | 5.9 | V | Maximum VCC, dV/dt = 1 V/ms, TA = 25°C, A1330 sampling enabled | 5 | |
| Supply Zener Clamp Voltage | VZSUP | 26.5 | V | ICC = ICC + 3 mA, TA = 25°C | 5 | ||
| Reverse-Battery Current | IRCC | 5 | mA | VRCC = 18 V, TA = 25°C | 5 | ||
| Output Load Resistance | RL | 4.7 | kΩ | VOUT to VCC | 5 | ||
| Output Current Limit | ILIMIT | 24 | 29 | 34 | mA | Minimum output, shorted to 5 V | 5 |
| Output Load Capacitance | COUT | 10 | nF | 5 | |||
| DAC Output Noise | ANOISE | 15 | mVp-p | DAC output, excluding angle measurement noise, 30 kHz BW setting | 5 | ||
| DAC Output Noise | ANOISE | 10 | mVp-p | DAC output, excluding angle measurement noise, 15 kHz BW setting | 5 | ||
| Analog Drift | /VDRIFT/ | 10 | 30 | mV | Absolute change in analog output from 25°C to 150°C | 5 | |
| Output Saturation Voltage (max) | VOUT(MAX) | 4.65 | 4.75 | V | Max input angle position; VCC = 5 V, HIGH_CLAMP = 0 | 6 | |
| Output Saturation Voltage (min) | VOUT(MIN) | 0.25 | 0.35 | V | 0° input angle position; VCC = 5 V, HIGH_CLAMP = 0 | 6 | |
| Clamp High | VCLAMP(H) | 32 | 95 | % VCC or DC | Valid for Analog or PWM output, EEPROM programmable | 6 | |
| Clamp Low | VCLAMP(L) | 5 | 68 | % VCC or DC | Valid for Analog or PWM output, EEPROM programmable | 6 | |
| Magnetic Field B Range | B | 1200 | G | Range of input field | 6 | ||
| Temperature Drift | ANGLEDRIFT | -1.8 | 0.5 | 1.8 | degrees | Angle change from 25°C; TA = 150°C, B = 300 G | 6 |
| Angle Error | ERRANG | -1.1 | 0.4 | 1.1 | degrees | TA = 25°C, ideal magnet alignment, B = 300 G | 6 |
| Angle Error | ERRANG | -1.5 | 0.5 | 1.5 | degrees | TA = 150°C, ideal magnet alignment, B = 300 G | 6 |
| Access Code Timeout | tACC | 70 | ms | Customer Access Code should be fully entered in less than tACC, measured from when VCC crosses VCC(UVH) | 13 | ||
| Baud Rate | fs | 5 | 40 | kbps | Defined by the input message bit rate sent from the external controller | 13 | |
| Bit Time Error | errTBIT | -15 | 15 | % | Deviation in tBIT during one command frame | 13 | |
| EEPROM Memory Write Delay | td(WRITE,E) | 40 | µs | Required delay from the trailing edge of the second EEPROM Programming pulse to the leading edge of a following command frame | 13 | ||
| Manchester Code High Voltage | VMAN(H) | 7.3 | V | Applied to VCC line | 13 | ||
| Manchester Code Low Voltage | VMAN(L) | 6.3 | V | Applied to VCC line | 13 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | in an 8-pin TSSOP. The package is lead (Pb) free with 100% matte-tin leadframe plating. | 1 |
CAD (KiCad official)
- Symbol:
A1330LLETR-T - Footprint:
Package_SO:TSSOP-8_4.4x3mm_P0.65mm - 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
a1330lletr-t-etched.step/a1330lletr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a1330lletr-t.step/a1330lletr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (40 pp, sha256
71ff967c2bb769fd, retrieved 2026-11-05, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).