component
TPS54362BQPWPRQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS54362BQPWPRQ1
Texas Instruments · DC-DC Converters · HTSSOP-20-EP
TPS54362BQPWPRQ1 from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NU | passive | Pin table says to connect this pin to ground, while the pin-configuration legend defines NU as make no external connection, so confirm before layout. |
| 2 | NU | unconnected | Not used; the pin-configuration legend states NU pins make no external connection. |
| 3 | SYNC | input | External synchronization clock input that overrides the internal oscillator clock, with an internal 62 kΩ (typical) pulldown to ground. |
| 4 | LPM | input | Low-power mode control driven by a digital input signal, with an internal 62 kΩ (typical) pulldown to ground. |
| 5 | EN | input | Enable pin, internally pulled up, that requires an external pullup or pulldown to enable or disable the device. |
| 6 | RT | output | External resistor to ground programs the internal oscillator frequency. |
| 7 | Rslew | output | External resistor to ground controls the slew rate of the internal switching FET. |
| 8 | RST | output | Active-low, open-drain reset output that connects to an external bias voltage through a resistor and is asserted high after the device starts regulating. |
| 9 | Cdly | bidirectional | External capacitor to ground programs the power-on-reset delay. |
| 10 | GND | power_in | Ground pin. |
| 11 | SS | bidirectional | External capacitor to ground programs the soft-start time. |
| 12 | OV_TH | input | Overvoltage sense input that monitors the regulated output as divided by the external resistor network between VReg and ground, which sets the threshold. |
| 13 | RST_TH | input | Undervoltage and reset sense input that monitors the regulated output as divided by the external resistor network between VReg and ground, which sets the threshold that initiates a reset-output signal. |
| 14 | VSENSE | input | Inverting node of the error amplifier for voltage-mode control. |
| 15 | COMP | bidirectional | Error-amplifier output that connects to external compensation components. |
| 16 | VReg | input | Internal low-side FET connection to load the output during start-up or to limit overshoot. |
| 17 | PH | output | Source of the internal switching FET. |
| 18 | VIN | power_in | Unregulated input voltage; pin 18 and pin 19 must be connected together externally. |
| 19 | VIN | power_in | Unregulated input voltage; pin 19 must be connected together with pin 18 externally. |
| 20 | BOOT | output | External bootstrap capacitor connects from BOOT to PH to drive the gate of the internal switching FET. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
TPS54362BQPWPRQ1 - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps54362bqpwprq1-etched.step/tps54362bqpwprq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54362bqpwprq1.step/tps54362bqpwprq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (44 pp, sha256
81197f9afad901c9, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).