component
RT7257BHZSP
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOIC-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownRT7257BHZSP
Richtek Tech · DC-DC Converters · SOIC-8-EP
RT7257BHZSP from Richtek Tech, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | power_in | Bootstrap for high-side gate driver. Connect a 0.1μF or greater ceramic capacitor from BOOT to SW. V(BOOT)-V(SW) absolute max 6V. |
| 2 | VIN | power_in | Input supply voltage, 4.5V to 18V (abs max 20V). Must be bypassed with a suitable large ceramic capacitor (e.g. 10μF x2 + 0.1μF). |
| 3 | SW | power_out | Switch node. Connect to an external L-C output filter. Swings between GND and VIN at up to 1.2MHz. High-side RDS(on) 110mΩ, low-side 90mΩ. |
| 4,9 | GND | power_in | Ground. Pin 4 and the exposed pad (pin 9) must both be soldered to a large PCB copper area connected to GND for maximum power dissipation (θJA 75°C/W with exposed pad). |
| 5 | FB | input | Feedback input. Regulates the output via an external resistive voltage divider. Internal reference VREF = 0.8V (±1.5%). |
| 6 | COMP | output | Compensation node for the regulation control loop. Connect a series R-C network from COMP to GND; an optional additional capacitor from COMP to GND may be required in some cases. |
| 7 | EN | input | Enable input. Logic high (VIH ≥ 2.7V) enables the converter; logic low (VIL ≤ 0.4V) puts the device into shutdown (<3μA supply). Tie to VIN via a 100kΩ pull-up for automatic startup. Absolute max 20V. |
| 8 | SS | input | Soft-start control input. Connect a capacitor from SS to GND to set the soft-start period; a 0.1μF cap gives ~13.5ms (ISS = 6μA typ). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOIC-8-EP |
| Category | PMIC |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
RT7257BHZSPRT7257BHZSPLZSP
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Input Voltage | VIN | -0.3 | 20 | V | 4 | ||
| Switch Voltage | VSW | -0.3 | V | Printed as (VIN + 0.3V); maximum is not a fixed number | 4 | ||
| VBOOT − VSW | VBOOT − VSW | -0.3 | 6 | V | 4 | ||
| Other Pins Voltage | -0.3 | 20 | V | 4 | |||
| Power Dissipation, SOP-8 (Exposed Pad) | PD | 1.333 | W | TA = 25°C | 4 | ||
| Package Thermal Resistance, SOP-8 (Exposed Pad) junction to ambient | θJA | 75 | °C/W | Note 2: TA = 25°C, four-layer JEDEC 51-7 test board | 4 | ||
| Package Thermal Resistance, SOP-8 (Exposed Pad) junction to case | θJC | 15 | °C/W | Measured at exposed pad | 4 | ||
| Lead Temperature (Soldering) | 260 | °C | 10 sec soldering | 4 | |||
| Junction Temperature | 150 | °C | 4 | ||||
| Storage Temperature Range | -65 | 150 | °C | 4 | |||
| ESD Susceptibility HBM | 2 | kV | Human Body Model | 4 | |||
| Supply Input Voltage | VIN | 4.5 | 18 | V | 4 | ||
| Junction Temperature Range | -40 | 125 | °C | 4 | |||
| Ambient Temperature Range | -40 | 85 | °C | 4 | |||
| Shutdown Supply Current | 0.5 | 3 | A | VEN = 0V | 4 | ||
| Supply Current | 0.8 | 1.2 | mA | VEN = 3V, VFB = 0.9V | 4 | ||
| Reference Voltage | VREF | 0.788 | 0.8 | 0.812 | V | 4.5V VIN 18V | 4 |
| High Side Switch Leakage Current | 0 | 10 | A | VEN = 0V, VSW = 0V | 4 | ||
| Oscillation Frequency | fOSC1 | 1 | 1.2 | 1.4 | MHz | 4 | |
| EN Input Threshold Logic-High Voltage | VIH | 2.7 | 18 | V | 5 | ||
| EN Input Threshold Logic-Low Voltage | VIL | 0.4 | V | 5 | |||
| Input Under Voltage Lockout Threshold | VUVLO | 3.8 | 4.2 | 4.5 | V | VIN Rising | 5 |
CAD (KiCad official)
- Symbol:
RT7257BHZSP - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
rt7257bhzsp-etched.step/rt7257bhzsp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt7257bhzsp.step/rt7257bhzsp.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
rt7257bhzsp.step |
125 KB | You want the bare part, or you mark your own boards. |
rt7257bhzsp-etched.step |
2.1 MB | You want the part with RT7257BHZSP already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 531 faces against 152 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (14 pp, sha256
f9aaf4883cb3a8fc, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).