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TUSB3410IRHBT

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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TUSB3410IRHBT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-32(5x5)

TUSB3410IRHBT from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREGEN input Active-low terminal that enables the 3.3-V to 1.8-V voltage regulator.
2 SUSPEND output Suspend indicator output; asserted high when the device is in suspend mode (3-state CMOS, ±12-mA drive and sink).
3 VCC power_in 3.3-V supply input (recommended supply range 3 V to 3.6 V).
4 VDD18 power_in 1.8-V supply; generated internally when VREGEN is low, and must be supplied externally when VREGEN is high.
5 PUR output Pullup resistor connection output (3-state CMOS, ±8-mA drive and sink).
6 DP bidirectional Upstream USB port differential data plus.
7 DM bidirectional Upstream USB port differential data minus.
8 GND power_in Digital ground.
9 RESET input Device master reset input (TTL-compatible input with hysteresis).
10 SDA bidirectional Master I2C controller data signal (TTL-compatible hysteresis input with internal 100-µA active pullup; 3-state CMOS output, ±4-mA drive and sink).
11 SCL output Master I2C controller clock signal (3-state CMOS output, ±4-mA drive and sink).
12 WAKEUP input Remote wake-up request input; when low, it wakes up the system (TTL-compatible input with hysteresis and internal 100-µA active pullup).
13 CTS input UART clear-to-send input (TTL-compatible input with hysteresis).
14 DSR input UART data-set-ready input (TTL-compatible input with hysteresis).
15 DCD input UART data-carrier-detect input (TTL-compatible input with hysteresis).
16 RI/CP input UART ring-indicator input (TTL-compatible input with hysteresis).
17 SIN/IR_SIN input UART serial data input, or IR serial data input (TTL-compatible input without hysteresis, with internal 100-µA active pullup).
18 GND power_in Digital ground.
19 SOUT/IR_SOUT output UART serial data output, or IR serial data output (3-state CMOS, ±4-mA drive and sink in normal or IR mode).
20 RTS output UART request-to-send output (3-state CMOS, ±4-mA drive and sink).
21 DTR output Active-low UART data-terminal-ready output (3-state CMOS, ±4-mA drive and sink).
22 CLKOUT output Clock output whose enable and source select are controlled by bits 2 (CLKOUTEN) and 3 (CLKSLCT) of the MODECNFG register.
23 TEST0 input Factory-test input that must be tied to VCC through a 10-kΩ resistor.
24 TEST1 input Factory-test input that must be tied to VCC through a 10-kΩ resistor (TTL-compatible input with hysteresis and internal 100-µA active pullup).
25 VCC power_in 3.3-V supply input (recommended supply range 3 V to 3.6 V).
26 X2 output 12-MHz crystal output.
27 X1/CLKI input 12-MHz crystal input or external clock input.
28 GND power_in Digital ground.
29 P3.4 bidirectional General-purpose I/O 4 (port 3, terminal 4); 3-state CMOS output with ±12-mA drive and sink, and treated by the MCU as open drain (driven low continuously, high driven for two clock cycles then high-impedance).
30 P3.3 bidirectional General-purpose I/O 3 (port 3, terminal 3); 3-state CMOS output with ±12-mA drive and sink, and treated by the MCU as open drain (driven low continuously, high driven for two clock cycles then high-impedance).
31 P3.1 bidirectional General-purpose I/O 1 (port 3, terminal 1); 3-state CMOS output with ±12-mA drive and sink, and treated by the MCU as open drain (driven low continuously, high driven for two clock cycles then high-impedance).
32 P3.0 bidirectional General-purpose I/O 0 (port 3, terminal 0); 3-state CMOS output with ±12-mA drive and sink, and treated by the MCU as open drain (driven low continuously, high driven for two clock cycles then high-impedance).
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32(5x5)
Category Embedded Processors & Controllers
Pins 33

CAD (KiCad official)

  • Symbol: TUSB3410IRHBT
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: tusb3410irhbt-etched.step / tusb3410irhbt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tusb3410irhbt.step / tusb3410irhbt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (107 pp, sha256 1ee2c8831308d541, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF