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MCP6N16-100E

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Microchip Tech Instrumentation Amplifiers, MSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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MCP6N16-100E

Microchip Tech · Instrumentation Amplifiers · MSOP-8

MCP6N16-100E from Microchip Tech, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable input is a CMOS Schmitt-triggered input: low puts the part in a low-power state, high lets it operate normally, and it must not be left floating.
2 VIM input Inverting analog signal input is a high-impedance CMOS input with low bias currents.
3 VIP input Non-inverting analog signal input is a high-impedance CMOS input with low bias currents.
4 VSS power_in Negative power supply, which is connected to ground in single-supply operation; VDD must be 1.8V to 5.5V above VSS and the other pins must stay between VSS and VDD.
5 VREF power_in Analog reference input (non-inverting input of the second stage) is a high-impedance CMOS input that shifts VOUT to its desired range, and the external gain resistor RG connects to it.
6 VFG input Analog feedback input (inverting input of the second stage) is a high-impedance CMOS input to which the external feedback components RF and RG connect.
7 VOUT output Analog output is a low impedance voltage output representing VDM = VIP - VIM with gain GDM and shifted by VREF, with the external feedback resistor RF connected to it.
8 VDD power_in Positive power supply, 1.8V to 5.5V higher than VSS, which needs bypass capacitors.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package MSOP-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Offset Voltage (GMIN = 100) VOS -17 17 µV TA = +25°C 4
Input Offset Voltage Drift, Linear Temp. Co. (GMIN = 100) TC1 -60 60 nV/°C TA = -40°C to +125°C (Note 2, design guidance only) 4
Power Supply Rejection Ratio (GMIN = 100) PSRR 110 128 dB 4
Input Bias Current IB -100 2 100 pA 5
Input Offset Current IOS -800 300 800 pA 5
Input Offset Current across temperature IOS -1500 350 1500 pA TA = +125°C 5
Common Mode Rejection Ratio (GMIN = 100) CMRR 103 121 dB VCM = VIVL to VIVH, VDD = 1.8V 5
Common Mode Rejection Ratio (GMIN = 100) CMRR 112 130 dB VCM = VIVL to VIVH, VDD = 5.5V 5
Common Mode Rejection Ratio at VREF (GMIN = 100) CMRR2 102 120 dB VREF = 0.2V to VDD, 0.2V, VDD = 1.8V 5
Common Mode Rejection Ratio at VREF (GMIN = 100) CMRR2 115 133 dB VREF = 0.2V to VDD, 0.2V, VDD = 5.5V 5
Common Mode Nonlinearity (GMIN = 100) INLCM -20 20 ppm VCM = VIVL to VIVH, VDD = 1.8V 6
Common Mode Nonlinearity (GMIN = 100) INLCM -10 10 ppm VCM = VIVL to VIVH, VDD = 5.5V 6
Differential Gain Error (GMIN = 100) gE -0.15 0.02 0.15 % VDD = 5.5V, VREF = 0.2V, VDM = 0 to (2.7V)/GMIN 6
DC Open-Loop Gain (GMIN = 100) AOL 108 126 dB VDD = 1.8V, VOUT = 0.2V to 1.6V 7
DC Open-Loop Gain (GMIN = 100) AOL 119 137 dB VDD = 5.5V, VOUT = 0.2V to 5.3V 7
Supply Voltage VDD 1.8 5.5 V 8
Quiescent Current per Amplifier IQ 0.5 1.1 1.6 mA IO = 0 8
POR Trip Voltage (falling) VPRL 0.9 1.27 V 8
POR Trip Voltage (rising) VPRH 1.33 1.6 V 8
GND Current ISS -8 -2 µA EN = 0V, VDD = 5.5V 11
EN Low to Amplifier Output High Z Turn-Off Time tOFF 0.1 2 µs EN = 0.2VDD to VOUT = 0.1(VDD/2), VL = 0V 11
EN High to Amplifier Output On Time tON 12 100 VDD = 1.8V, EN = 0.8VDD to VOUT = 0.9(VDD/2), VL = 0V 11
EN High to Amplifier Output On Time tON 30 100 VDD = 5.5V, EN = 0.8VDD to VOUT = 0.9(VDD/2), VL = 0V 11
EN Low to EN High hold time tENLH 50 Minimum time before releasing EN (Note 1, design guidance only) 11
EN High to EN Low setup time tENHL 50 Minimum time before exerting EN (Note 1, design guidance only) 11
ESD protection (HBM) 4 kV HBM 3
ESD protection (MM) 400 V MM 3
Supply voltage across VDD, VSS (absolute maximum) VDD -VSS 6.5 V 3
Current at Input Pins -2 2 mA 3
Current at Output and Supply Pins -30 30 mA 3
Storage Temperature -65 150 °C 3
Maximum Junction Temperature 150 °C 3
Specified Temperature Range TA -40 125 °C 12
Operating Temperature Range TA -40 125 °C Operation must not cause TJ to exceed +150°C (Note 1) 12
Thermal Resistance, 8L-MSOP θJA 211 °C/W 12

CAD (KiCad official)

  • Symbol: MCP6N16-100E
  • Footprint: Package_SO:MSOP-8_3x3mm_P0.65mm
  • 3D model: MSOP-8 (KiCad packages3D, STEP)
  • 3D model files: mcp6n16-100e-etched.step / mcp6n16-100e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp6n16-100e.step / mcp6n16-100e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (58 pp, sha256 fc250dadec3d573c, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF