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CBM24AD99Q

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Corebai Microelectronics Analog To Digital Converters (ADC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CBM24AD99Q

Corebai Microelectronics · Analog To Digital Converters (ADC) · TQFP-64(10x10)

CBM24AD99Q from Corebai Microelectronics, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN8N input Differential analog negative input 8 (CBM24AD99Q only); connect unused analog inputs directly to AVDD.
2 IN8P input Differential analog positive input 8 (CBM24AD99Q only); connect unused analog inputs directly to AVDD.
3 IN7N input Differential analog negative input 7 (CBM24AD99Q only); connect unused analog inputs directly to AVDD.
4 IN7P input Differential analog positive input 7 (CBM24AD99Q only); connect unused analog inputs directly to AVDD.
5 IN6N input Differential analog negative input 6 (CBM24AD99Q-6 and CBM24AD99Q only); connect unused analog inputs directly to AVDD.
6 IN6P input Differential analog positive input 6 (CBM24AD99Q-6 and CBM24AD99Q only); connect unused analog inputs directly to AVDD.
7 IN5N input Differential analog negative input 5 (CBM24AD99Q-6 and CBM24AD99Q only); connect unused analog inputs directly to AVDD.
8 IN5P input Differential analog positive input 5 (CBM24AD99Q-6 and CBM24AD99Q only); connect unused analog inputs directly to AVDD.
9 IN4N input Differential analog negative input 4; connect unused analog inputs directly to AVDD.
10 IN4P input Differential analog positive input 4; connect unused analog inputs directly to AVDD.
11 IN3N input Differential analog negative input 3; connect unused analog inputs directly to AVDD.
12 IN3P input Differential analog positive input 3; connect unused analog inputs directly to AVDD.
13 IN2N input Differential analog negative input 2; connect unused analog inputs directly to AVDD.
14 IN2P input Differential analog positive input 2; connect unused analog inputs directly to AVDD.
15 IN1N input Differential analog negative input 1; connect unused analog inputs directly to AVDD.
16 IN1P input Differential analog positive input 1; connect unused analog inputs directly to AVDD.
17 SRB1 bidirectional Stimulus, reference and bias signal 1, routable to the inverting inputs of all channels.
18 SRB2 bidirectional Stimulus, reference and bias signal 2, routable to the positive input of selected channels.
19 AVDD power_in Analog supply; connect a 1 µF capacitor to AVSS.
20 AVSS power_in Analog ground.
21 AVDD power_in Analog supply; connect a 1 µF capacitor to AVSS.
22 AVDD power_in Analog supply; connect a 1 µF capacitor to AVSS.
23 AVSS power_in Analog ground.
24 VREFP bidirectional Positive analog reference voltage; connect a minimum 10 µF capacitor to VREFN.
25 VREFN input Negative analog reference voltage; connect to AVSS when using the internal reference.
26 VCAP4 passive Analog bypass capacitor pin; connect a 1 µF capacitor to AVSS.
27 NC unconnected No connection; leave open.
28 VCAP1 passive Analog bypass capacitor pin; connect a 100 µF capacitor to AVSS.
29 NC unconnected No connection; leave open.
30 VCAP2 passive Analog bypass capacitor pin; connect a 1 µF capacitor to AVSS.
31 RESV1 input Reserved for future use; connect directly to DGND.
32 AVSS power_in Analog ground.
33 DGND power_in Digital ground.
34 DIN input Serial data input.
35 PWDN input Power-down, active low (PWDN_).
36 RESET input System reset, active low (RESET_).
37 CLK input Master clock input (external clock 1.5 to 2.25 MHz, typically 2.048 MHz, when CLKSEL = 0).
38 START input Synchronization signal to start or restart conversions.
39 CS input Chip select, active low (CS_).
40 SCLK input Serial clock input.
41 DAISY_IN input Daisy-chain input.
42 GPIO1 bidirectional General-purpose I/O pin 1; if unused, connect to DGND with a resistor of at least 10 kΩ.
43 DOUT tri_state Serial data output (high impedance when CS_ is high).
44 GPIO2 bidirectional General-purpose I/O pin 2; if unused, connect to DGND with a resistor of at least 10 kΩ.
45 GPIO3 bidirectional General-purpose I/O pin 3; if unused, connect to DGND with a resistor of at least 10 kΩ.
46 GPIO4 bidirectional General-purpose I/O pin 4; if unused, connect to DGND with a resistor of at least 10 kΩ.
47 DRDY output Data ready, active low (DRDY_).
48 DVDD power_in Digital supply; connect a 1 µF capacitor to DGND.
49 DGND power_in Digital ground.
50 DVDD power_in Digital supply; connect a 1 µF capacitor to DGND.
51 DGND power_in Digital ground.
52 CLKSEL input Master clock select (0 = external clock, 1 = internal oscillator); tie high to DVDD or low to DGND through a resistor of at least 10 kΩ.
53 AVSS1 power_in Analog ground.
54 AVDD1 power_in Analog supply; connect a 1 µF capacitor to AVSS1.
55 VCAP3 passive Analog bypass capacitor pin; connect a parallel combination of 1 µF and 0.1 µF capacitors to AVSS.
56 AVDD power_in Analog supply; connect a 1 µF capacitor to AVSS.
57 AVSS power_in Analog ground.
58 AVSS power_in Charge-pump analog ground.
59 AVDD power_in Charge-pump analog supply; connect a 1 µF capacitor to AVSS (pin 58).
60 BIASREF input Bias drive non-inverting input.
61 BIASINV bidirectional Bias drive inverting input.
62 BIASIN input Bias drive input to the MUX.
63 BIASOUT output Bias drive output.
64 Reserved unconnected Reserved for future use (analog output); leave open.

Key specifications

Parameter Value
Manufacturer Corebai Microelectronics
Package TQFP-64(10x10)
Category Data Acquisition
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD to AVSS -0.3 5.5 V 6
DVDD to DGND -0.3 3.9 V 6
AVSS to DGND -3 0.2 V 6
Continuous input current, any pin except supply pins -10 10 mA 6
Junction temperature TJ 150 ℃ 6
Storage temperature Tstg -60 150 ℃ 6
ESD HBM V(ESD) -1000 1000 V ANSI/ESDA/JEDEC JS-001 6
Analog supply AVDD to AVSS AVDD 4.75 5 5.25 V 6
Digital supply DVDD to DGND DVDD 1.8 1.8 3.6 V 6
Analog to digital supply AVDD - DVDD -2.1 3.6 V 6
Reference input voltage VREF 4.5 V VREF = VVREFP - VVREFN 6
External clock frequency fCLK 1.5 2.048 2.25 MHz CLKSEL pin = 0 6
Digital input voltage -0.1 V DGND-0.1 to DVDD+0.1 6
Operating temperature TA -40 85 ℃ 6
Junction-to-ambient thermal resistance RθJA 46.2 ℃/W PAG (TQFP) 64 pin 7
Junction-to-case (top) thermal resistance RθJC(top) 5.8 ℃/W PAG (TQFP) 64 pin 7
Junction-to-board thermal resistance RθJB 19.6 ℃/W PAG (TQFP) 64 pin 7
Input bias current -300 300 pA TA = +25°C, InxP and INxN = 2.5V 7
Input capacitance 20 pF 7
Data rate DR 250 16000 SPS fCLK = 2.048 MHz 7
Input-referred noise (0.01 Hz to 70 Hz) 1 1.35 μVPP 250 points, 1 s data, gain = 24, TA = +25°C 7
Input-referred noise (0.01 Hz to 70 Hz) 1 1.6 μVPP 250 points, 1 s data, gain = 24, TA = -40°C to +85°C 7
Gain error -0.5 0.1 0.5 % of FS Excluding voltage reference error 7
Offset error 60 μV 7
Offset error drift 80 nV/°C 7
Gain drift 3 ppm/°C Excluding voltage reference drift 7
Internal reference accuracy VREF -0.2 0.2 % Internal reference 4.5 V 8
Internal reference drift 35 ppm/°C TA = -40°C to +85°C 8
Internal clock accuracy -0.5 0.5 % TA = +25°C 8
Internal clock accuracy -2.5 2.5 % TA = -40°C to +85°C 8
High-level input voltage (min) VIH 0.8 DVDD DVDD = 1.8 V to 3.6 V; min 0.8 DVDD 8
Low-level input voltage (min) VIL -0.1 V DVDD = 1.8 V to 3.6 V 8
High-level output voltage VOH 0.9 DVDD IOH = -500 μA 8
Low-level output voltage VOL 0.1 DVDD IOL = +500 μA 8
Digital input current -10 10 μA 0 V < VDigitalInput < DVDD 8
AVDD supply current IAVDD 7.14 mA Normal mode, AVDD - AVSS = 5V 8

CAD (KiCad official)

  • Symbol: CBM24AD99Q
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: cbm24ad99q-etched.step / cbm24ad99q-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cbm24ad99q.step / cbm24ad99q.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Corebai Microelectronics datasheet (42 pp, sha256 7724ef787ba0b234, retrieved 2026-10-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF