component
UCC38C43DGKR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VSSOP-8-0.65mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownUCC38C43DGKR
Texas Instruments · DC-DC Converters · VSSOP-8-0.65mm
UCC38C43DGKR from Texas Instruments, in a VSSOP-8-0.65mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | This pin provides the output of the error amplifier for compensation and is internally current-limited so zero duty cycle can be commanded by forcing COMP to GND, with error amplifier output sink current limited to 10 mA maximum. |
| 2 | FB | input | FB is the inverting input of the error amplifier, whose noninverting input is internally trimmed to 2.5V ±1%. |
| 3 | CS | input | Primary-side current sense input connected to the noninverting input of the PWM comparator, which terminates OUT conduction, with analog input voltage limited to -0.3 V to 6.3 V. |
| 4 | RT/CT | bidirectional | Fixed-frequency oscillator timing node where timing resistor RRT connects to VREF and timing capacitor CCT connects to GND to set the switching frequency, with analog input voltage limited to -0.3 V to 6.3 V. |
| 5 | GND | power_in | Ground return pin for the output driver stage and the logic-level controller section, to which all voltages are referenced. |
| 6 | OUT | output | Totem-pole output intended to directly drive a MOSFET, sourcing and sinking up to 1 A peak, with a driver voltage range of -0.3 V to 20 V, and actively held low when VDD is below the turn-on threshold. |
| 7 | VDD | power_in | Analog controller bias and power input with an absolute maximum of 20 V, which has no internal clamp and therefore must be protected from exceeding 20 V, and which requires a 0.1 µF ceramic bypass to GND placed as close to the pin as possible. |
| 8 | VREF | power_in | 5 V reference output that requires a minimum 0.1 µF ceramic bypass capacitor placed as close to the pin as possible, has a 55 mA maximum output short-circuit current, and must not be pulled to ground to terminate switching. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8-0.65mm |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
UCC38C43DGKR - Footprint:
Package_SO:VSSOP-8_2.3x2mm_P0.5mm - 3D model: VSSOP-8-0.65mm (KiCad packages3D, STEP)
- 3D model files:
ucc38c43dgkr-etched.step/ucc38c43dgkr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc38c43dgkr.step/ucc38c43dgkr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (60 pp, sha256
9fa55f996731c56b, retrieved 2026-10-10, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).