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74VHC126PW

Public Made by Adom

by adom

Nexperia Buffers, Drivers, Receivers, Transceivers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74VHC126PW

Nexperia · Buffers, Drivers, Receivers, Transceivers · TSSOP-14

74VHC126PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable input for buffer 1, active HIGH; a LOW level puts output 1Y into the high-impedance OFF-state.
2 1A input Data input for buffer 1; the inputs have Schmitt-trigger action and accept voltages up to 5.5 V (VI range 0 to 5.5 V).
3 1Y tri_state Data output of buffer 1 with 3-state behaviour; it is high-impedance when 1OE is LOW and its voltage range is 0 to VCC.
4 2OE input Output enable input for buffer 2, active HIGH; a LOW level puts output 2Y into the high-impedance OFF-state.
5 2A input Data input for buffer 2; the inputs have Schmitt-trigger action and accept voltages up to 5.5 V (VI range 0 to 5.5 V).
6 2Y tri_state Data output of buffer 2 with 3-state behaviour; it is high-impedance when 2OE is LOW and its voltage range is 0 to VCC.
7 GND power_in Ground (0 V) reference for all voltages on the device.
8 3Y tri_state Data output of buffer 3 with 3-state behaviour; it is high-impedance when 3OE is LOW and its voltage range is 0 to VCC.
9 3A input Data input for buffer 3; the inputs have Schmitt-trigger action and accept voltages up to 5.5 V (VI range 0 to 5.5 V).
10 3OE input Output enable input for buffer 3, active HIGH; a LOW level puts output 3Y into the high-impedance OFF-state.
11 4Y tri_state Data output of buffer 4 with 3-state behaviour; it is high-impedance when 4OE is LOW and its voltage range is 0 to VCC.
12 4A input Data input for buffer 4; the inputs have Schmitt-trigger action and accept voltages up to 5.5 V (VI range 0 to 5.5 V).
13 4OE input Output enable input for buffer 4, active HIGH; a LOW level puts output 4Y into the high-impedance OFF-state.
14 VCC power_in Supply voltage: 2.0 V to 5.5 V for 74VHC126, and 4.5 V to 5.5 V for 74VHCT126 (recommended operating range).

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VCC -0.5 7 V 3
Input voltage (absolute maximum) VI -0.5 7 V 3
Input clamping current IIK -20 mA VI < -0.5 V 3
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 3
Output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 3
Supply current (absolute maximum) ICC 75 mA 3
Ground current IGND -75 mA 3
Storage temperature Tstg -65 150 °C 3
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 3
Supply voltage (recommended, 74VHC126) VCC 2 5 5.5 V 3
Input voltage (recommended) VI 0 5.5 V 3
Output voltage (recommended) VO 0 V 3
Ambient temperature (recommended) Tamb -40 25 125 °C 3
Input transition rise and fall rate Δt/ΔV 100 ns/V VCC = 3.0 V to 3.6 V 3
Input transition rise and fall rate Δt/ΔV 20 ns/V VCC = 4.5 V to 5.5 V 3
HIGH-level input voltage VIH 1.5 V VCC = 2.0 V 4
HIGH-level input voltage VIH 2.1 V VCC = 3.0 V 4
HIGH-level input voltage VIH 3.85 V VCC = 5.5 V 4
LOW-level input voltage VIL 0.5 V VCC = 2.0 V 4
LOW-level input voltage VIL 0.9 V VCC = 3.0 V 4
LOW-level input voltage VIL 1.65 V VCC = 5.5 V 4
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V 4
HIGH-level output voltage VOH 2.9 3 V VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V 4
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V 4
HIGH-level output voltage VOH 2.58 V VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V; Tamb = 25 °C 4
HIGH-level output voltage VOH 3.94 V VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V; Tamb = 25 °C 4
HIGH-level output voltage VOH 2.4 V VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V; Tamb = -40 °C to +125 °C 4
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V; Tamb = -40 °C to +125 °C 4
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V 4
LOW-level output voltage VOL 0.36 V VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V; Tamb = 25 °C 4
LOW-level output voltage VOL 0.55 V VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V; Tamb = -40 °C to +125 °C 4
Input leakage current II 0.1 μA VI = 5.5 V or GND; VCC = 0 V to 5.5 V; Tamb = 25 °C 4
Input leakage current II 2 μA VI = 5.5 V or GND; VCC = 0 V to 5.5 V; Tamb = -40 °C to +125 °C 4
OFF-state output current IOZ -0.25 0.25 μA VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V; Tamb = 25 °C 4
OFF-state output current IOZ -10 10 μA VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V; Tamb = -40 °C to +125 °C 4
Supply current ICC 2 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb = 25 °C 4
Supply current ICC 40 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb = -40 °C to +125 °C 4
Input capacitance CI 3 10 pF VI = VCC or GND 4
Propagation delay nA to nY tpd 1 4.7 10 ns VCC = 3.0 V to 3.6 V; CL = 15 pF; Tamb = -40 °C to +125 °C 5
Propagation delay nA to nY tpd 1 6.7 14.5 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; Tamb = -40 °C to +125 °C 5
Propagation delay nA to nY tpd 1 3.3 7 ns VCC = 4.5 V to 5.5 V; CL = 15 pF; Tamb = -40 °C to +125 °C 5
Propagation delay nA to nY tpd 1 4.7 9.5 ns VCC = 4.5 V to 5.5 V; CL = 50 pF; Tamb = -40 °C to +125 °C 5
Enable time nOE to nY ten 1 5.3 10 ns VCC = 3.0 V to 3.6 V; CL = 15 pF; Tamb = -40 °C to +125 °C 5
Enable time nOE to nY ten 1 7.6 14.5 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; Tamb = -40 °C to +125 °C 5
Enable time nOE to nY ten 1 3.6 7 ns VCC = 4.5 V to 5.5 V; CL = 15 pF; Tamb = -40 °C to +125 °C 5
Enable time nOE to nY ten 1 5.1 9.5 ns VCC = 4.5 V to 5.5 V; CL = 50 pF; Tamb = -40 °C to +125 °C 5
Disable time nOE to nY tdis 1 6.6 12.5 ns VCC = 3.0 V to 3.6 V; CL = 15 pF; Tamb = -40 °C to +125 °C 5
Disable time nOE to nY tdis 1 9.4 16.5 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; Tamb = -40 °C to +125 °C 5
Disable time nOE to nY tdis 1 4.7 8.5 ns VCC = 4.5 V to 5.5 V; CL = 15 pF; Tamb = -40 °C to +125 °C 5
Disable time nOE to nY tdis 1 6.7 11 ns VCC = 4.5 V to 5.5 V; CL = 50 pF; Tamb = -40 °C to +125 °C 5

CAD (KiCad official)

  • Symbol: 74VHC126PW
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74vhc126pw-etched.step / 74vhc126pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74vhc126pw.step / 74vhc126pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (14 pp, sha256 4c3aded1c4236a66, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF