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74HCT165D
Public Made by Adomby adom
Nexperia Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdown74HCT165D
Nexperia · Shift Registers · SOIC-16
74HCT165D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PL | input | Asynchronous parallel load input (active LOW); when LOW, data on D0 to D7 is loaded into the shift register asynchronously. |
| 2 | CP | input | Clock input, LOW-to-HIGH edge-triggered; data is shifted on LOW-to-HIGH transitions when CE is LOW. |
| 3 | D4 | input | Parallel data input D4 (Dn), loaded into the register when PL is LOW. |
| 4 | D5 | input | Parallel data input D5 (Dn), loaded into the register when PL is LOW. |
| 5 | D6 | input | Parallel data input D6 (Dn), loaded into the register when PL is LOW. |
| 6 | D7 | input | Parallel data input D7 (Dn), loaded into the register when PL is LOW. |
| 7 | ~{Q7} | output | Complementary output from the last stage of the shift register. |
| 8 | GND | power_in | Ground (0 V). |
| 9 | Q7 | output | Serial output from the last stage of the shift register. |
| 10 | DS | input | Serial data input; when PL is HIGH, data enters the register serially at this pin. |
| 11 | D0 | input | Parallel data input D0 (Dn), loaded into the register when PL is LOW. |
| 12 | D1 | input | Parallel data input D1 (Dn), loaded into the register when PL is LOW. |
| 13 | D2 | input | Parallel data input D2 (Dn), loaded into the register when PL is LOW. |
| 14 | D3 | input | Parallel data input D3 (Dn), loaded into the register when PL is LOW. |
| 15 | CE | input | Clock enable input (active LOW); a HIGH on CE disables the CP input. |
| 16 | VCC | power_in | Positive supply voltage; for 74HCT165 the recommended range is 4.5 V to 5.5 V (Table 5, page 5). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | 4.5 | 5 | 5.5 | V | 5 | |
| input voltage | VI | 0 | V | 5 | |||
| output voltage | VO | 0 | V | 5 | |||
| ambient temperature | Tamb | -40 | 125 | °C | 5 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 5 | |
| supply voltage | VCC | -0.5 | 7 | V | 5 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 5 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 5 | |
| output current | IO | -25 | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 5 | |
| supply current | ICC | 50 | mA | 5 | |||
| ground current | IGND | -50 | mA | 5 | |||
| storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 5 | ||
| HIGH-level input voltage | VIH | 2 | 1.6 | V | VCC = 4.5 V to 5.5 V; 25 °C | 6 | |
| HIGH-level input voltage | VIH | 2 | V | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 6 | ||
| LOW-level input voltage | VIL | 1.2 | 0.8 | V | VCC = 4.5 V to 5.5 V; 25 °C | 6 | |
| LOW-level input voltage | VIL | 0.8 | V | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 6 | ||
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; 25 °C | 6 | |
| HIGH-level output voltage | VOH | 4.4 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; -40 °C to +125 °C | 6 | ||
| HIGH-level output voltage | VOH | 3.98 | 4.32 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; 25 °C | 6 | |
| HIGH-level output voltage | VOH | 3.7 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; -40 °C to +125 °C | 6 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 4.5 V; 25 °C | 6 | |
| LOW-level output voltage | VOL | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 4.5 V; -40 °C to +125 °C | 6 | ||
| LOW-level output voltage | VOL | 0.16 | 0.26 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; 25 °C | 6 | |
| LOW-level output voltage | VOL | 0.4 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; -40 °C to +125 °C | 6 | ||
| input leakage current | II | -0.1 | 0.1 | μA | VI = VCC or GND; VCC = 6.0 V; 25 °C | 6 | |
| input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 6 | |
| supply current | ICC | 8 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; 25 °C | 6 | ||
| supply current | ICC | 160 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 6 | ||
| additional supply current (Dn and DS inputs) | ΔICC | 35 | 126 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; 25 °C | 6 | |
| additional supply current (Dn and DS inputs) | ΔICC | 171.5 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 6 | ||
| additional supply current (CP, CE and PL inputs) | ΔICC | 65 | 234 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; 25 °C | 6 | |
| additional supply current (CP, CE and PL inputs) | ΔICC | 318.5 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 6 | ||
| propagation delay CE, CP to Q7, Q7 | tpd | 17 | 34 | ns | CE, CP to Q7, Q7; see Fig. 5; VCC = 4.5 V; CL = 50 pF; 25 °C | 8 | |
| propagation delay CE, CP to Q7, Q7 | tpd | 51 | ns | CE, CP to Q7, Q7; see Fig. 5; VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C | 8 | ||
| propagation delay PL to Q7, Q7 | tpd | 20 | 40 | ns | PL to Q7, Q7; see Fig. 6; VCC = 4.5 V; CL = 50 pF; 25 °C | 8 | |
| propagation delay PL to Q7, Q7 | tpd | 60 | ns | PL to Q7, Q7; see Fig. 6; VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C | 8 | ||
| propagation delay D7 to Q7, Q7 | tpd | 14 | 28 | ns | D7 to Q7, Q7; see Fig. 7; VCC = 4.5 V; CL = 50 pF; 25 °C | 8 | |
| propagation delay D7 to Q7, Q7 | tpd | 42 | ns | D7 to Q7, Q7; see Fig. 7; VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C | 8 | ||
| transition time Q7, Q7 output | tt | 7 | 15 | ns | Q7, Q7 output; see Fig. 5; VCC = 4.5 V; CL = 50 pF; 25 °C | 9 | |
| transition time Q7, Q7 output | tt | 22 | ns | Q7, Q7 output; see Fig. 5; VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C | 9 | ||
| pulse width CP input HIGH or LOW | tW | 16 | 6 | ns | CP input HIGH or LOW; see Fig. 5; VCC = 4.5 V; 25 °C | 9 | |
| pulse width CP input HIGH or LOW | tW | 24 | ns | CP input HIGH or LOW; see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C | 9 | ||
| pulse width PL input LOW | tW | 20 | 9 | ns | PL input LOW; see Fig. 6; VCC = 4.5 V; 25 °C | 9 | |
| pulse width PL input LOW | tW | 30 | ns | PL input LOW; see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C | 9 | ||
| recovery time PL to CP, CE | trec | 20 | 8 | ns | PL to CP, CE; see Fig. 6; VCC = 4.5 V; 25 °C | 9 | |
| recovery time PL to CP, CE | trec | 30 | ns | PL to CP, CE; see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C | 9 | ||
| set-up time DS to CP, CE | tsu | 20 | 2 | ns | DS to CP, CE; see Fig. 8; VCC = 4.5 V; 25 °C | 9 | |
| set-up time DS to CP, CE | tsu | 30 | ns | DS to CP, CE; see Fig. 8; VCC = 4.5 V; -40 °C to +125 °C | 9 | ||
| set-up time CE to CP and CP to CE | tsu | 20 | 7 | ns | CE to CP and CP to CE; see Fig. 8; VCC = 4.5 V; 25 °C | 9 | |
| set-up time CE to CP and CP to CE | tsu | 30 | ns | CE to CP and CP to CE; see Fig. 8; VCC = 4.5 V; -40 °C to +125 °C | 9 | ||
| set-up time Dn to PL | tsu | 20 | 10 | ns | Dn to PL; see Fig. 9; VCC = 4.5 V; 25 °C | 9 | |
| set-up time Dn to PL | tsu | 30 | ns | Dn to PL; see Fig. 9; VCC = 4.5 V; -40 °C to +125 °C | 9 | ||
| hold time DS to CP, CE and Dn to PL | th | 7 | -1 | ns | DS to CP, CE and Dn to PL; see Fig. 8; VCC = 4.5 V; 25 °C | 9 | |
| hold time DS to CP, CE and Dn to PL | th | 11 | ns | DS to CP, CE and Dn to PL; see Fig. 8; VCC = 4.5 V; -40 °C to +125 °C | 9 | ||
| hold time CE to CP and CP to CE | th | 0 | -7 | ns | CE to CP and CP to CE; see Fig. 8; VCC = 4.5 V; 25 °C | 9 | |
| hold time CE to CP and CP to CE | th | 0 | ns | CE to CP and CP to CE; see Fig. 8; VCC = 4.5 V; -40 °C to +125 °C | 9 | ||
| maximum frequency CP input | fmax | 26 | 44 | MHz | CP input; see Fig. 5; VCC = 4.5 V; 25 °C | 9 | |
| maximum frequency CP input | fmax | 17 | MHz | CP input; see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C | 9 |
CAD (KiCad official)
- Symbol:
74HCT165D - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
74hct165d-etched.step/74hct165d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hct165d.step/74hct165d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (18 pp, sha256
376fad78107f38d0, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).