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CD4023BM

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HGSEMI Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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CD4023BM

HGSEMI · Logic Gates · SOIC-14

CD4023BM from HGSEMI, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 2A input Data input A of NAND gate 2; input voltage must stay between -0.5 V and VDD+0.5 V and DC input current is limited to ±10 mA (absolute maximum ratings).
2 2B input Data input B of NAND gate 2; input voltage must stay between -0.5 V and VDD+0.5 V and DC input current is limited to ±10 mA (absolute maximum ratings).
3 1A input Data input A of NAND gate 1; input voltage must stay between -0.5 V and VDD+0.5 V and DC input current is limited to ±10 mA (absolute maximum ratings).
4 1B input Data input B of NAND gate 1; input voltage must stay between -0.5 V and VDD+0.5 V and DC input current is limited to ±10 mA (absolute maximum ratings).
5 1C input Data input C of NAND gate 1; input voltage must stay between -0.5 V and VDD+0.5 V and DC input current is limited to ±10 mA (absolute maximum ratings). Unused inputs must be connected to VDD, GND, or another input.
6 1Y output Fully buffered output of NAND gate 1, specified for VDD from 3 V to 15 V.
7 GND power_in Ground reference (0 V); all device voltages are referenced to this pin.
8 2C input Data input C of NAND gate 2; input voltage must stay between -0.5 V and VDD+0.5 V and DC input current is limited to ±10 mA (absolute maximum ratings).
9 2Y output Fully buffered output of NAND gate 2, specified for VDD from 3 V to 15 V.
10 3Y output Fully buffered output of NAND gate 3, specified for VDD from 3 V to 15 V.
11 3C input Data input C of NAND gate 3; input voltage must stay between -0.5 V and VDD+0.5 V and DC input current is limited to ±10 mA (absolute maximum ratings).
12 3B input Data input B of NAND gate 3; input voltage must stay between -0.5 V and VDD+0.5 V and DC input current is limited to ±10 mA (absolute maximum ratings).
13 3A input Data input A of NAND gate 3; input voltage must stay between -0.5 V and VDD+0.5 V and DC input current is limited to ±10 mA (absolute maximum ratings).
14 VDD power_in Supply voltage, recommended range 3 V to 15 V referenced to GND; absolute maximum supply voltage is 18 V.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VDD -0.5 18 V 3
DC input current IIK -10 10 mA any one input 3
input voltage VI -0.5 V all inputs 3
storage temperature Tstg -65 150 ℃ 3
total power dissipation Ptot 500 mW 3
device dissipation P 100 mW per output transistor 3
supply voltage VDD 3 15 V 3
ambient temperature Tamb -40 105 ℃ in free air 3
supply current IDD 0.01 0.25 uA VO=-; VIN=0,5; VDD=5V; Tamb=25℃ 4
supply current IDD 0.01 0.5 uA VO=-; VIN=0,10; VDD=10V; Tamb=25℃ 4
supply current IDD 0.01 1 uA VO=-; VIN=0,15; VDD=15V; Tamb=25℃ 4
LOW-level output current IOL 0.51 1 mA VO=0.4; VIN=0,5; VDD=5V; Tamb=25℃ 4
LOW-level output current IOL 1.3 2.6 mA VO=0.5; VIN=0,10; VDD=10V; Tamb=25℃ 4
LOW-level output current IOL 3.4 6.8 mA VO=1.5; VIN=0,15; VDD=15V; Tamb=25℃ 4
HIGH-level output current IOH -0.51 -1 mA VO=4.6; VIN=0,5; VDD=5V; Tamb=25℃ 4
HIGH-level output current IOH -1.6 -3.2 mA VO=2.5; VIN=0,5; VDD=5V; Tamb=25℃ 4
HIGH-level output current IOH -1.3 -2.6 mA VO=9.5; VIN=0,10; VDD=10V; Tamb=25℃ 4
HIGH-level output current IOH -3.4 -6.8 mA VO=13.5; VIN=0,15; VDD=15V; Tamb=25℃ 4
LOW-level output voltage VOL 0 0.05 V VIN=0,5; VDD=5V; Tamb=25℃ 4
HIGH-level output voltage VOH 4.95 5 V VIN=0,5; VDD=5V; Tamb=25℃ 4
HIGH-level output voltage VOH 9.95 10 V VIN=0,10; VDD=10V; Tamb=25℃ 4
HIGH-level output voltage VOH 14.95 15 V VIN=0,15; VDD=15V; Tamb=25℃ 4
LOW-level input voltage VIL 1.5 V VO=0.5,4.5; VDD=5V; Tamb=25℃ 4
LOW-level input voltage VIL 3 V VO=1,9; VDD=10V; Tamb=25℃ 4
LOW-level input voltage VIL 4 V VO=1.5,13.5; VDD=15V; Tamb=25℃ 4
HIGH-level input voltage VIH 3.5 V VO=4.5; VDD=5V; Tamb=25℃ 4
HIGH-level input voltage VIH 7 V VO=9; VDD=10V; Tamb=25℃ 4
HIGH-level input voltage VIH 11 V VO=13.5; VDD=15V; Tamb=25℃ 4
supply current IDD 7.5 uA VO=-; VIN=0,5; VDD=5V; Tamb=+105℃ 5
supply current IDD 15 uA VO=-; VIN=0,10; VDD=10V; Tamb=+105℃ 5
supply current IDD 30 uA VO=-; VIN=0,15; VDD=15V; Tamb=+105℃ 5
LOW-level output current IOL 0.36 mA VO=0.4; VIN=0,5; VDD=5V; Tamb=+105℃ 5
LOW-level output current IOL 0.9 mA VO=0.5; VIN=0,10; VDD=10V; Tamb=+105℃ 5
LOW-level output current IOL 2.4 mA VO=1.5; VIN=0,15; VDD=15V; Tamb=+105℃ 5
HIGH-level output current IOH -0.36 mA VO=4.6; VIN=0,5; VDD=5V; Tamb=+105℃ 5
HIGH-level output current IOH -1.15 mA VO=2.5; VIN=0,5; VDD=5V; Tamb=+105℃ 5
HIGH-level output current IOH -0.9 mA VO=9.5; VIN=0,10; VDD=10V; Tamb=+105℃ 5
HIGH-level output current IOH -2.4 mA VO=13.5; VIN=0,15; VDD=15V; Tamb=+105℃ 5
LOW-level output voltage VOL 0.05 V VIN=0,5; VDD=5V; Tamb=+105℃ 5
HIGH-level output voltage VOH 4.95 V VIN=0,5; VDD=5V; Tamb=+105℃ 5
HIGH-level output voltage VOH 9.95 V VIN=0,10; VDD=10V; Tamb=+105℃ 5
HIGH-level output voltage VOH 14.95 V VIN=0,15; VDD=15V; Tamb=+105℃ 5
LOW-level input voltage VIL 1.5 V VO=4.5; VDD=5V; Tamb=+105℃ 5
LOW-level input voltage VIL 3 V VO=9; VDD=10V; Tamb=+105℃ 5
LOW-level input voltage VIL 4 V VO=13.5; VDD=15V; Tamb=+105℃ 5
HIGH-level input voltage VIH 3.5 V VO=0.5,4.5; VDD=5V; Tamb=+105℃ 5
HIGH-level input voltage VIH 7 V VO=1.9; VDD=10V; Tamb=+105℃ 5
HIGH-level input voltage VIH 11 V VO=1.5,13.5; VDD=15V; Tamb=+105℃ 5
input leakage current II -1 1 uA VO=-; VIN=0,15; VDD=15V; Tamb=+105℃ 5
propagation delay time tPHL, tPLH 125 250 ns see Figure 4; VDD=5V 5
propagation delay time tPHL, tPLH 60 120 ns see Figure 4; VDD=10V 5
propagation delay time tPHL, tPLH 45 90 ns see Figure 4; VDD=15V 5
transition time tTHL, tTLH 100 200 ns see Figure 4; VDD=5V 5
transition time tTHL, tTLH 50 100 ns see Figure 4; VDD=10V 5
transition time tTHL, tTLH 40 80 ns see Figure 4; VDD=15V 5
input capacitance CI 5 7.5 pF any input 5

CAD (KiCad official)

  • Symbol: CD4023BM
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd4023bm-etched.step / cd4023bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4023bm.step / cd4023bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (10 pp, sha256 e160e18d36027181, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF