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SN74HCT374PWR

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Texas Instruments Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74HCT374PWR

Texas Instruments · Flip Flops · TSSOP-20

SN74HCT374PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low output-enable input; when HIGH all eight Q outputs enter the high-impedance state; TTL-voltage compatible, VIH min 2 V, VIL max 0.8 V, max input current 1 μA.
2 1Q tri_state 3-state registered output of flip-flop 1; set to the D1 level on the rising edge of CLK; ±6 mA drive at 5 V, VOH min 3.7 V / VOL max 0.4 V at 6 mA load.
3 1D input Data input for flip-flop 1; sampled on the positive transition of CLK; TTL-voltage compatible, setup time 25 ns min, hold time 10 ns min at VCC = 4.5 V.
4 2D input Data input for flip-flop 2; sampled on the positive transition of CLK; TTL-voltage compatible, setup time 25 ns min, hold time 10 ns min at VCC = 4.5 V.
5 2Q tri_state 3-state registered output of flip-flop 2; set to the D2 level on the rising edge of CLK; ±6 mA drive at 5 V, VOH min 3.7 V / VOL max 0.4 V at 6 mA load.
6 3Q tri_state 3-state registered output of flip-flop 3; set to the D3 level on the rising edge of CLK; ±6 mA drive at 5 V, VOH min 3.7 V / VOL max 0.4 V at 6 mA load.
7 3D input Data input for flip-flop 3; sampled on the positive transition of CLK; TTL-voltage compatible, setup time 25 ns min, hold time 10 ns min at VCC = 4.5 V.
8 4D input Data input for flip-flop 4; sampled on the positive transition of CLK; TTL-voltage compatible, setup time 25 ns min, hold time 10 ns min at VCC = 4.5 V.
9 4Q tri_state 3-state registered output of flip-flop 4; set to the D4 level on the rising edge of CLK; ±6 mA drive at 5 V, VOH min 3.7 V / VOL max 0.4 V at 6 mA load.
10 GND power_in Ground supply reference, 0 V; continuous current through GND pin must not exceed ±70 mA.
11 CLK input Common positive-edge clock input for all eight flip-flops; data captured on rising edge; max clock frequency 25 MHz at VCC = 4.5 V, pulse width min 20 ns.
12 5Q tri_state 3-state registered output of flip-flop 5; set to the D5 level on the rising edge of CLK; ±6 mA drive at 5 V, VOH min 3.7 V / VOL max 0.4 V at 6 mA load.
13 5D input Data input for flip-flop 5; sampled on the positive transition of CLK; TTL-voltage compatible, setup time 25 ns min, hold time 10 ns min at VCC = 4.5 V.
14 6D input Data input for flip-flop 6; sampled on the positive transition of CLK; TTL-voltage compatible, setup time 25 ns min, hold time 10 ns min at VCC = 4.5 V.
15 6Q tri_state 3-state registered output of flip-flop 6; set to the D6 level on the rising edge of CLK; ±6 mA drive at 5 V, VOH min 3.7 V / VOL max 0.4 V at 6 mA load.
16 7Q tri_state 3-state registered output of flip-flop 7; set to the D7 level on the rising edge of CLK; ±6 mA drive at 5 V, VOH min 3.7 V / VOL max 0.4 V at 6 mA load.
17 7D input Data input for flip-flop 7; sampled on the positive transition of CLK; TTL-voltage compatible, setup time 25 ns min, hold time 10 ns min at VCC = 4.5 V.
18 8D input Data input for flip-flop 8; sampled on the positive transition of CLK; TTL-voltage compatible, setup time 25 ns min, hold time 10 ns min at VCC = 4.5 V.
19 8Q tri_state 3-state registered output of flip-flop 8; set to the D8 level on the rising edge of CLK; ±6 mA drive at 5 V, VOH min 3.7 V / VOL max 0.4 V at 6 mA load.
20 VCC power_in Positive supply voltage, 4.5 V to 5.5 V recommended; max ICC 80 μA at VCC = 5.5 V; decouple with 0.1 μF ceramic capacitor placed close to pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74HCT374PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74hct374pwr-etched.step / sn74hct374pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hct374pwr.step / sn74hct374pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 de341c7e9d1699a1, retrieved 2026-09-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-4-6 (text+vision), consensus claude-opus-4-7 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF