CS4350-CZZR from Cirrus Logic, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DIF2(AD1/CDOUT)	bidirectional	Digital Interface Format bit 2 in stand-alone mode; address bit 1 in I²C mode, or data output in SPI mode.
2	DEM(AD0/CS)	input	De-emphasis select for the 15 µs/50 µs filter response at 44.1 kHz sample rates in stand-alone mode; address bit 0 in I²C mode or chip select in SPI mode.
3	DIF0(SDA/CDIN)	bidirectional	Digital Interface Format bit 0 in stand-alone mode; serial control data I/O for I²C and data input for SPI.
4	DIF1(SCL/CCLK)	input	Digital Interface Format bit 1 in stand-alone mode; serial control port clock input for the control interface.
5	VLC	power_in	Positive power for the hardware/software control interface; recommended range 3.14 V to 5.25 V.
6	VD_FILT	power_out	Filter connection for the internal voltage regulator.
7	GND	power_in	Ground reference.
8	RMCK	output	Recovered master clock output derived from LRCK; output frequency depends on VLS.
9	VLS	power_in	Positive power for the serial audio interface; recommended range 1.35 V to 5.25 V.
10	SCLK	input	Serial bit-clock input for the serial audio interface.
11	SDIN	input	Serial audio data input for two's complement serial audio data.
12	LRCK	input	Left/right clock input that determines which channel, Left or Right, is active on the serial audio data line.
13	TSTO	unconnected	Test output; this pin must be left floating and not connected to any trace or plane.
14	AOUTA-	output	Differential analog output (negative leg) for channel A; the full-scale output level is specified in the DAC Analog Characteristics table on page 9.
15	AOUTA+	output	Differential analog output (positive leg) for channel A; the full-scale output level is specified in the DAC Analog Characteristics table on page 9.
16	AMUTEC	output	Mute control output for channel A, providing control signals for an optional mute circuit.
17	VBIAS+	power_out	Positive voltage reference output serving as the positive reference voltage for the internal DAC.
18	VA	power_in	Positive analog power supply; recommended range 4.75 V to 5.25 V (5.0 V nominal) or 3.14 V to 3.46 V (3.3 V nominal).
19	GND	power_in	Ground reference.
20	VQ	power_out	Filter connection for the internal quiescent voltage, which the datasheet specifies as -0.5•VA VDC.
21	BMUTEC	output	Mute control output for channel B, providing control signals for an optional mute circuit.
22	AOUTB+	output	Differential analog output (positive leg) for channel B; the full-scale output level is specified in the DAC Analog Characteristics table on page 9.
23	AOUTB-	output	Differential analog output (negative leg) for channel B; the full-scale output level is specified in the DAC Analog Characteristics table on page 9.
24	RST	input	Reset input; when pulled low, the device powers down and resets all internal registers to their default settings.

Key specifications

Parameter	Value
Manufacturer	Cirrus Logic
Package	TSSOP-24
Category	ADC/DAC/Data Conversion
Pins	24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Analog power	VA	4.75	5	5.25	V		8
Analog power	VA	3.14	3.3	3.46	V		8
Serial Audio Interface power	VLS	1.35	3.3	5.25	V		8
Control Interface power	VLC	3.14	3.3	5.25	V		8
Ambient Operating Temperature (Power Applied), Commercial	TA	-40		85	°C	Power applied; Commercial (-CZZ,-CNZ)	8
Analog power	VA	-0.3		6	V		8
Serial Audio Interface power	VLS	-0.3		6	V		8
Control Interface power	VLC	-0.3		6	V		8
Input Current	Iin	-10		10	mA	Any pin except supplies (Note 3)	8
Digital Input Voltage, Serial Audio Interface	VIN-LS	-0.3			V	Maximum printed as VLS + 0.4 V	8
Digital Input Voltage, Control Interface	VIN-LC	-0.3			V	Maximum printed as VLC + 0.4 V	8
Ambient Operating Temperature (power applied)	TA	-55		125	°C	Power applied	8
Storage Temperature	Tstg	-65		150	°C		8
Interchannel Gain Mismatch			0.1	0.25	dB	VA = 3.3 to 5.0 V	9
Full Scale Output Voltage - Single Ended (-CZZ)		2.61	2.78	2.96	Vpp	VA = 3.3 to 5.0 V; Commercial -CZZ	9
Full Scale Output Voltage - Differential (-CZZ)		5.22	5.56	5.92	Vpp	VA = 3.3 to 5.0 V; Commercial -CZZ	9
High-Level Input Voltage	VIH	2			V	VLC or VLS = 3.3 V	16
High-Level Input Voltage	VIH	1.7			V	VLS = 2.5 V	16
Low-Level Input Voltage	VIL			0.8	V	VLC or VLS = 3.3 V	16
Low-Level Input Voltage	VIL			0.7	V	VLS = 2.5 V	16
Input Leakage Current	Iin	-10		10	A		16
Low Level Output Voltage (RMCK)	VOL			0.4	V	IO = -2 mA (VLS >= 3.0 V)	16
RMCK Output Load Drive				10	pF		16
Power Supply Current - Normal Operation, analog	IA		28	34	mA	VA = 5.0 V; Fs = 48 kHz (Note 17)	16
Power Supply Current - Normal Operation, analog	IA		24	29	mA	VA = 3.3 V; Fs = 48 kHz (Note 17)	16
Power Supply Current - Normal Operation, serial audio	ILS		4	6	mA	VLS = VLC = 5.0 V (Note 18)	16
Power Supply Current - Normal Operation, serial audio	ILS		2	5	mA	VLS = VLC = 3.3 V (Note 18)	16
Power Supply Current - Normal Operation, control interface	ILC		14	18	mA	VLS = VLC = 5.0 V (Note 19)	16
Power Dissipation - Normal Operation			230	290	mW	VA = VLC = VLS = 5.0 V (Note 17)	16
Power Dissipation - Normal Operation			132	171	mW	VA = VLC = VLS = 3.3 V (Note 17)	16
RMCK Output Frequency		7.68		16.896	MHz	VLS = 1.62 V or above	13
RMCK Output Frequency		7.68		55.3	MHz	VLS = 2.97 V or above	13
RMCK Output Duty Cycle		45		55	%	3.14 V <= VA <= 5.25 V and 1.35 V <= VLS <= 5.25 V	13
Input Sample Rate, Single-Speed Mode		30		54	kHz	3.14 V <= VA <= 5.25 V and 1.35 V <= VLS <= 5.25 V	13
Input Sample Rate, Double-Speed Mode	Fs	60		108	kHz	3.14 V <= VA <= 5.25 V and 1.35 V <= VLS <= 5.25 V	13
Input Sample Rate, Quad-Speed Mode		120		216	kHz	3.14 V <= VA <= 5.25 V and 1.35 V <= VLS <= 5.25 V	13
LRCK Duty Cycle (Non-TDM Mode)		40		60	%	3.14 V <= VA <= 5.25 V and 1.35 V <= VLS <= 5.25 V	13
SDIN Setup Time Before SCLK Rising Edge	tds	1			ns	3.14 V <= VA <= 5.25 V and 1.35 V <= VLS <= 5.25 V	13
SDIN Hold Time After SCLK Rising Edge	tdh	8			ns	3.14 V <= VA <= 5.25 V and 1.35 V <= VLS <= 5.25 V	13
SCLK Frequency				55.3	MHz	4.75 V <= VA <= 5.25 V and 3.14 V <= VLS <= 5.25 V	13
SCLK High Time	tsckh	6			ns	4.75 V <= VA <= 5.25 V and 3.14 V <= VLS <= 5.25 V	13
SCLK Low Time	tsckl	6			ns	4.75 V <= VA <= 5.25 V and 3.14 V <= VLS <= 5.25 V	13
LRCK Edge to SCLK Rising Edge (Non-TDM)	tlcks	11			ns	4.75 V <= VA <= 5.25 V and 3.14 V <= VLS <= 5.25 V	13
SCLK Rising Edge to LRCK Edge (Non-TDM)	tlckd	1			ns	4.75 V <= VA <= 5.25 V and 3.14 V <= VLS <= 5.25 V	13
LRCK High Time (TDM)	tlrckh	20			ns	4.75 V <= VA <= 5.25 V and 3.14 V <= VLS <= 5.25 V	13
SCLK Rising to LRCK Falling Edge (TDM)	tfsh	3			ns	4.75 V <= VA <= 5.25 V and 3.14 V <= VLS <= 5.25 V	13
LRCK Rising Edge to SCLK Rising Edge (TDM)	tfss	1			ns	4.75 V <= VA <= 5.25 V and 3.14 V <= VLS <= 5.25 V	13
SCLK Frequency				27.7	MHz	3.14 V <= VA < 4.75 V or 1.35 V <= VLS < 3.14 V	13
SCLK High Time	tsckh	11			ns	3.14 V <= VA < 4.75 V or 1.35 V <= VLS < 3.14 V	13
SCLK Low Time	tsckl	11			ns	3.14 V <= VA < 4.75 V or 1.35 V <= VLS < 3.14 V	13
LRCK Edge to SCLK Rising Edge (Non-TDM)	tlcks	16			ns	3.14 V <= VA < 4.75 V or 1.35 V <= VLS < 3.14 V	13
LRCK High Time (TDM)	tlrckh	25			ns	3.14 V <= VA < 4.75 V or 1.35 V <= VLS < 3.14 V	13
SCLK Rising to LRCK Falling Edge (TDM)	tfsh	8			ns	3.14 V <= VA < 4.75 V or 1.35 V <= VLS < 3.14 V	13
Package Thermal Resistance - TSSOP Single-Layer PCB	JA		105		°C/Watt	Single-layer PCB	40
Package Thermal Resistance - TSSOP Multiple-Layer PCB	JA		70		°C/Watt	Multiple-layer PCB	40

CAD (KiCad official)

Symbol: CS4350-CZZR
Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
3D model: TSSOP-24 (KiCad packages3D, STEP)
3D model files: cs4350-czzr-etched.step / cs4350-czzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs4350-czzr.step / cs4350-czzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Cirrus Logic datasheet (41 pp, sha256 4f7dd59cb055103c, retrieved 2026-11-05, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CS4350-CZZR

Verified CS4350-CZZR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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