Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

74HC245N

HGSEMI · Buffers, Drivers, Receivers, Transceivers · DIP-20

74HC245N from HGSEMI, in a DIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIR input Transmission direction control input that selects the direction of data transfer between the A and B ports.
2 A0 bidirectional Data input/output port A0 of the 8-bit bus transceiver, with three-state outputs.
3 A1 bidirectional Data input/output port A1 of the 8-bit bus transceiver, with three-state outputs.
4 A2 bidirectional Data input/output port A2 of the 8-bit bus transceiver, with three-state outputs.
5 A3 bidirectional Data input/output port A3 of the 8-bit bus transceiver, with three-state outputs.
6 A4 bidirectional Data input/output port A4 of the 8-bit bus transceiver, with three-state outputs.
7 A5 bidirectional Data input/output port A5 of the 8-bit bus transceiver, with three-state outputs.
8 A6 bidirectional Data input/output port A6 of the 8-bit bus transceiver, with three-state outputs.
9 A7 bidirectional Data input/output port A7 of the 8-bit bus transceiver, with three-state outputs.
10 GND power_in Ground (0 V) reference for the device.
11 B7 bidirectional Data input/output port B7 of the 8-bit bus transceiver, with three-state outputs.
12 B6 bidirectional Data input/output port B6 of the 8-bit bus transceiver, with three-state outputs.
13 B5 bidirectional Data input/output port B5 of the 8-bit bus transceiver, with three-state outputs.
14 B4 bidirectional Data input/output port B4 of the 8-bit bus transceiver, with three-state outputs.
15 B3 bidirectional Data input/output port B3 of the 8-bit bus transceiver, with three-state outputs.
16 B2 bidirectional Data input/output port B2 of the 8-bit bus transceiver, with three-state outputs.
17 B1 bidirectional Data input/output port B1 of the 8-bit bus transceiver, with three-state outputs.
18 B0 bidirectional Data input/output port B0 of the 8-bit bus transceiver, with three-state outputs.
19 OE input Active-low output enable input; when driven high, the A and B ports are placed in the high-impedance (Z) state.
20 VCC power_in Supply voltage; recommended operating range 2.0 V to 6.0 V, with an absolute maximum of 7.0 V.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package DIP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 4
Input clamp current Ilk -20 20 mA VI<-0.5V or VI>Vcc+0.5V 4
Output clamp current Iok -20 20 mA Vo<-0.5V or Vo>Vcc+0.5V 4
Output or input/output current Io -35 35 mA -0.5V<Vo<Vcc+0.5V 4
VCC or GND current ICC, IGND -70 70 mA 4
Storage temperature Tstg -65 150 ℃ 4
Power dissipation, DIP20 package PD 750 mW DIP20 package (note 1) 4
Soldering temperature TL 260 ℃ 10 s 4
Supply voltage VCC 2 5 6 V 4
Input voltage VI 0 V maximum printed as Vcc 4
Output voltage Vo 0 V maximum printed as Vcc 4
Operating ambient temperature Tamb -40 85 ℃ 4
Input rise and fall time tr, tf 1000 ns VCC=2.0V 4
Input rise and fall time tr, tf 6 500 ns VCC=4.5V 4
Input rise and fall time tr, tf 400 ns VCC=6.0V 4
High-level input voltage VIH 1.5 1.2 V Tamb=25℃, GND=0; VCC=2.0V 5
High-level input voltage VIH 3.15 2.4 V Tamb=25℃, GND=0; VCC=4.5V 5
High-level input voltage VIH 4.2 3.2 V Tamb=25℃, GND=0; VCC=6.0V 5
Low-level input voltage VIL 0.8 0.5 V Tamb=25℃, GND=0; VCC=2.0V 5
Low-level input voltage VIL 2.1 1.35 V Tamb=25℃, GND=0; VCC=4.5V 5
Low-level input voltage VIL 2.8 1.8 V Tamb=25℃, GND=0; VCC=6.0V 5
High-level output voltage VOH 1.9 2 V Tamb=25℃; VI=VIH or VIL; VCC=2.0V, IO=-20uA 5
High-level output voltage VOH 4.4 4.5 V Tamb=25℃; VI=VIH or VIL; VCC=4.5V, IO=-20uA 5
High-level output voltage VOH 5.9 6 V Tamb=25℃; VI=VIH or VIL; VCC=6.0V, IO=-20uA 5
High-level output voltage VOH 3.98 4.32 V Tamb=25℃; VI=VIH or VIL; VCC=4.5V, IO=-6.0mA 5
High-level output voltage VOH 5.7 6 V Tamb=25℃; VI=VIH or VIL; VCC=6.0V, IO=-4mA 5
Low-level output voltage VOL 0 0.1 V Tamb=25℃; VI=VIH or VIL; VCC=2.0V, IO=20uA 5
Low-level output voltage VOL 0.15 0.3 V Tamb=25℃; VI=VIH or VIL; VCC=4.5V, IO=6.0mA 5
Low-level output voltage VOL 0.16 0.3 V Tamb=25℃; VI=VIH or VIL; VCC=6.0V, IO=4mA 5
Input leakage current ILI -1 0.1 1 uA Tamb=25℃; VI=VCC or GND, VCC=6.0V 5
Off-state output current IOZ -5 5 uA Tamb=25℃; VI=VIH or VIL, Vo=VCC or GND, VCC=6.0V 5
Quiescent supply current ICC -1 10 uA Tamb=25℃; VI=VCC or GND, VCC=6.0V, IO=0 5
Propagation delay An to Bn or Bn to An tPHL/tPLH 25 900 ns Tamb=25℃, CL=50pF, tr=tf=6ns; VCC=2.0V; Fig.4 7
Propagation delay An to Bn or Bn to An tPHL/tPLH 9 18 ns Tamb=25℃, CL=50pF, tr=tf=6ns; VCC=4.5V; Fig.4 7
Propagation delay An to Bn or Bn to An tPHL/tPLH 7 15 ns Tamb=25℃, CL=50pF, tr=tf=6ns; VCC=6.0V; Fig.4 7
Output transition time tTHL/tTLH 14 60 ns Tamb=25℃, CL=50pF, tr=tf=6ns; VCC=2.0V 7
Output transition time tTHL/tTLH 5 12 ns Tamb=25℃, CL=50pF, tr=tf=6ns; VCC=4.5V 7
Output transition time tTHL/tTLH 4 10 ns Tamb=25℃, CL=50pF, tr=tf=6ns; VCC=6.0V 7
Output enable time to high or low level tPZH/tPZl 30 150 ns Tamb=25℃, CL=50pF, tr=tf=6ns; VCC=2.0V; Fig.5 7
Output enable time to high or low level tPZH/tPZl 11 30 ns Tamb=25℃, CL=50pF, tr=tf=6ns; VCC=4.5V; Fig.5 7
Output enable time to high or low level tPZH/tPZl 9 26 ns Tamb=25℃, CL=50pF, tr=tf=6ns; VCC=6.0V; Fig.5 7
Output disable time to high or low level tPHZ/tPLZ 41 150 ns Tamb=25℃, CL=50pF, tr=tf=6ns; VCC=2.0V 7
Output disable time to high or low level tPHZ/tPLZ 15 30 ns Tamb=25℃, CL=50pF, tr=tf=6ns; VCC=4.5V 7
Output disable time to high or low level tPHZ/tPLZ 12 26 ns Tamb=25℃, CL=50pF, tr=tf=6ns; VCC=6.0V 7
High-level input voltage VIH 4.2 V Tamb=-40~+85℃; VCC=6.0V 6
Low-level input voltage VIL 1.8 V Tamb=-40~+85℃; VCC=6.0V 6
High-level output voltage VOH 5.9 V Tamb=-40~+85℃; VI=VIH or VIL; VCC=6.0V, IO=-20uA 6
High-level output voltage VOH 5.34 V Tamb=-40~+85℃; VI=VIH or VIL; VCC=6.0V, IO=-4mA 6
Low-level output voltage VOL 0.1 V Tamb=-40~+85℃; VI=VIH or VIL; VCC=6.0V, IO=20uA 6
Low-level output voltage VOL 0.33 V Tamb=-40~+85℃; VI=VIH or VIL; VCC=6.0V, IO=4mA 6
Input leakage current ILI -1 1 uA Tamb=-40~+85℃; VI=VCC or GND, VCC=6.0V 6
Off-state output current IOZ -5 5 uA Tamb=-40~+85℃; VI=VIH or VIL, Vo=VCC or GND, VCC=6.0V 6
Quiescent supply current ICC 80 uA Tamb=-40~+85℃; VI=VCC or GND, VCC=6.0V, IO=0 6
Propagation delay An to Bn or Bn to An tPHL/tPLH 20 ns Tamb=-40~+85℃, CL=50pF, tr=tf=6ns; VCC=6.0V; Fig.4 8
Output enable time to high or low level tPZH/tPZl 33 ns Tamb=-40~+85℃, CL=50pF, tr=tf=6ns; VCC=6.0V; Fig.5 8
Output disable time to high or low level tPHZ/tPLZ 33 ns Tamb=-40~+85℃, CL=50pF, tr=tf=6ns; VCC=6.0V 8
Quiescent supply current ICC 160 uA Tamb=-40~+125℃; VI=VCC or GND, VCC=6.0V, IO=0 7

CAD (KiCad official)

  • Symbol: 74HC245N
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: DIP-20 (KiCad packages3D, STEP)
  • 3D model files: 74hc245n-etched.step / 74hc245n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc245n.step / 74hc245n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (14 pp, sha256 430f66157c4aa735, retrieved 2026-10-14, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF