component

850S1201BGILFT

Public Made by Adom

by adom

RENESAS Clock Buffers, Drivers, Distributors, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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850S1201BGILFT

RENESAS · Clock Buffers, Drivers, Distributors · TSSOP-20

850S1201BGILFT from RENESAS, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLK8 input Single-ended clock input with LVCMOS/LVTTL interface levels and an internal pulldown resistor.
2 CLK9 input Single-ended clock input with LVCMOS/LVTTL interface levels and an internal pulldown resistor.
3 CLK10 input Single-ended clock input with LVCMOS/LVTTL interface levels and an internal pulldown resistor.
4 CLK11 input Single-ended clock input with LVCMOS/LVTTL interface levels and an internal pulldown resistor.
5 VDD power_in Power supply pin; the datasheet specifies 3.135V to 3.465V for 3.3V ±5% operation or 2.375V to 2.625V for 2.5V ±5% operation.
6 CLK_SEL0 input Clock select input (LSB of the 4-bit select code) with LVCMOS/LVTTL interface levels and an internal pulldown resistor.
7 CLK_SEL1 input Clock select input with LVCMOS/LVTTL interface levels and an internal pulldown resistor.
8 CLK_SEL2 input Clock select input with LVCMOS/LVTTL interface levels and an internal pulldown resistor.
9 CLK_SEL3 input Clock select input (MSB of the 4-bit select code) with LVCMOS/LVTTL interface levels and an internal pulldown resistor.
10 OE input Output enable pin for the Q output with LVCMOS/LVTTL interface levels and an internal pullup resistor.
11 Q output Single-ended clock output with LVCMOS/LVTTL interface levels; output impedance is 20 at VDD = 3.3V ±5% and 25 at VDD = 2.5V ±5%.
12 GND power_in Power supply ground.
13 CLK0 input Single-ended clock input with LVCMOS/LVTTL interface levels and an internal pulldown resistor.
14 CLK1 input Single-ended clock input with LVCMOS/LVTTL interface levels and an internal pulldown resistor.
15 CLK2 input Single-ended clock input with LVCMOS/LVTTL interface levels and an internal pulldown resistor.
16 CLK3 input Single-ended clock input with LVCMOS/LVTTL interface levels and an internal pulldown resistor.
17 CLK4 input Single-ended clock input with LVCMOS/LVTTL interface levels and an internal pulldown resistor.
18 CLK5 input Single-ended clock input with LVCMOS/LVTTL interface levels and an internal pulldown resistor.
19 CLK6 input Single-ended clock input with LVCMOS/LVTTL interface levels and an internal pulldown resistor.
20 CLK7 input Single-ended clock input with LVCMOS/LVTTL interface levels and an internal pulldown resistor.

Key specifications

Parameter Value
Manufacturer RENESAS
Package TSSOP-20
Category Clock/Timing
Pins 20

CAD (KiCad official)

  • Symbol: 850S1201BGILFT
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 850s1201bgilft-etched.step / 850s1201bgilft-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 850s1201bgilft.step / 850s1201bgilft.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (14 pp, sha256 f35cb54ca34ca9d4, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF