CY62148ELL-55SXI from Cypress Semicon, in a SOIC-32. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	A17	input	Address input A17 selecting one of the 512K memory locations.
2	A16	input	Address input A16 selecting one of the 512K memory locations.
3	A14	input	Address input A14 selecting one of the 512K memory locations.
4	A12	input	Address input A12 selecting one of the 512K memory locations.
5	A7	input	Address input A7 selecting one of the 512K memory locations.
6	A6	input	Address input A6 selecting one of the 512K memory locations.
7	A5	input	Address input A5 selecting one of the 512K memory locations.
8	A4	input	Address input A4 selecting one of the 512K memory locations.
9	A3	input	Address input A3 selecting one of the 512K memory locations.
10	A2	input	Address input A2 selecting one of the 512K memory locations.
11	A1	input	Address input A1 selecting one of the 512K memory locations.
12	A0	input	Address input A0 selecting one of the 512K memory locations.
13	I/O0	tri_state	Data I/O0, high impedance when deselected (CE HIGH), outputs disabled (OE HIGH) or during a write.
14	I/O1	tri_state	Data I/O1, high impedance when deselected (CE HIGH), outputs disabled (OE HIGH) or during a write.
15	I/O2	tri_state	Data I/O2, high impedance when deselected (CE HIGH), outputs disabled (OE HIGH) or during a write.
16	VSS	power_in	Ground pin, 0 V reference for the supply.
17	I/O3	tri_state	Data I/O3, high impedance when deselected (CE HIGH), outputs disabled (OE HIGH) or during a write.
18	I/O4	tri_state	Data I/O4, high impedance when deselected (CE HIGH), outputs disabled (OE HIGH) or during a write.
19	I/O5	tri_state	Data I/O5, high impedance when deselected (CE HIGH), outputs disabled (OE HIGH) or during a write.
20	I/O6	tri_state	Data I/O6, high impedance when deselected (CE HIGH), outputs disabled (OE HIGH) or during a write.
21	I/O7	tri_state	Data I/O7, high impedance when deselected (CE HIGH), outputs disabled (OE HIGH) or during a write.
22	CE	input	Active-low chip enable; HIGH deselects the device and puts it in standby/power-down.
23	A10	input	Address input A10 selecting one of the 512K memory locations.
24	OE	input	Active-low output enable; HIGH places the I/O pins in high impedance.
25	A11	input	Address input A11 selecting one of the 512K memory locations.
26	A9	input	Address input A9 selecting one of the 512K memory locations.
27	A8	input	Address input A8 selecting one of the 512K memory locations.
28	A13	input	Address input A13 selecting one of the 512K memory locations.
29	WE	input	Active-low write enable; taken LOW with CE LOW to write, HIGH for read.
30	A18	input	Address input A18 selecting one of the 512K memory locations.
31	A15	input	Address input A15 selecting one of the 512K memory locations.
32	VCC	power_in	Power supply, 4.5 V to 5.5 V operating range.

Key specifications

Parameter	Value
Manufacturer	Cypress Semicon
Package	SOIC-32
Category	Electronic Tools/Instruments/Consumables
Pins	32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Output HIGH voltage (VCC = 4.5 V, IOH = -1 mA)	VOH	2.4			V	VCC = 4.5 V, IOH = -1 mA	5
Output HIGH voltage (VCC = 5.5 V, IOH = -0.1 mA)	VOH			3.4	V	VCC = 5.5 V, IOH = -0.1 mA	5
Output LOW voltage	VOL			0.4	V	IOL = 2.1 mA	5
Input HIGH voltage	VIH	2.2			V	VCC = 4.5 V to 5.5 V	5
Input LOW voltage (SOIC package)	VIL	-0.5		0.6	V	VCC = 4.5 V to 5.5 V, For SOIC package	5
Input leakage current	IIX	-1		1	µA	GND < VI < VCC	5
Output leakage current	IOZ	-1		1	µA	GND < VO < VCC, output disabled	5
VCC operating supply current (fmax)	ICC		15	20	mA	f = fmax = 1/tRC, VCC = VCC(max), IOUT = 0 mA, CMOS levels	5
VCC operating supply current (1 MHz)	ICC		3.5	6	mA	f = 1 MHz	5
Automatic CE power-down current, CMOS inputs	ISB2		2.5	7	µA	CE > VCC, 0.2 V, VIN > VCC, 0.2 V or VIN < 0.2 V, f = 0, VCC = VCC(max)	5
VCC for data retention	VDR	2			V		7
Data retention current	ICCDR		3	8.8	µA	VCC = VDR, CE > VCC, 0.2 V, VIN > VCC, 0.2 V or VIN < 0.2 V	7
Chip deselect to data retention time	tCDR	0			ns		7
Operation recovery time (55 ns bin)	tR	55			ns		7
Read cycle time	tRC	55			ns		8
Address to data valid	tAA			55	ns		8
Data hold from address change	tOHA	10			ns		8
CE LOW to data valid	tACE			55	ns		8
OE LOW to data valid	tDOE			25	ns		8
OE LOW to low Z	tLZOE	5			ns		8
OE HIGH to high Z	tHZOE			20	ns		8
CE LOW to low Z	tLZCE	10			ns		8
CE HIGH to high Z	tHZCE			20	ns		8
CE LOW to power-up	tPU	0			ns		8
CE HIGH to power-down	tPD			55	ns		8
Write cycle time	tWC	55			ns		8
CE LOW to write end	tSCE	40			ns		8
Address setup to write end	tAW	40			ns		8
Address hold from write end	tHA	0			ns		8
Address setup to write start	tSA	0			ns		8
WE pulse width	tPWE	40			ns		8
Data setup to write end	tSD	25			ns		8
Data hold from write end	tHD	0			ns		8
WE LOW to high Z	tHZWE			20	ns		8
WE HIGH to low Z	tLZWE	10			ns		8
Input capacitance	CIN			10	pF	TA = 25 °C, f = 1 MHz, VCC = VCC(Typ)	6
Output capacitance	COUT			10	pF		6
Supply voltage (VCC) operating range	VCC	4.5		5.5	V		5
Ambient temperature (Industrial)		-40		85	°C		5
Storage temperature		-65		150	°C		5
Ambient temperature with power applied		-55		125	°C		5
Supply voltage to ground potential		-0.5		6	V		5
DC voltage applied to outputs in high Z state		-0.5		6	V		5
DC input voltage		-0.5		6	V		5
Output current into outputs (LOW)				20	mA		5
Static discharge voltage		2001			V	per MIL-STD-883, Method 3015	5
Latch-up current		200			mA		5
Thermal resistance, junction to ambient (32-pin SOIC)	JA		51.57		°C/W	Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board	6
Thermal resistance, junction to case (32-pin SOIC)	JC		25.01		°C/W		6

CAD (KiCad official)

Symbol: CY62148ELL-55SXI
Footprint: Package_SO:SOIC-32_7.518x20.777mm_P1.27mm
3D model: SOIC-32, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: cy62148ell-55sxi-etched.step / cy62148ell-55sxi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy62148ell-55sxi.step / cy62148ell-55sxi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Cypress Semicon datasheet (20 pp, sha256 609e28364a300e8e, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CY62148ELL-55SXI

Verified CY62148ELL-55SXI

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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