component
TMS320F28031PNT
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTMS320F28031PNT
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)
TMS320F28031PNT from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO22/EQEP1S/LINTXA | bidirectional | General-purpose I/O 22, default GPIO after reset with internal pull-up enabled; alternates are eQEP1 strobe (I/O) and LIN transmit (O); inputs are not 5 V tolerant. |
| 2 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32; alternates are I2C-A data (open-drain I/O), ePWM sync input and ADC SOCA output; inputs are not 5 V tolerant. |
| 3 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33; alternates are I2C-A clock (open-drain I/O), ePWM sync output and ADC SOCB output; inputs are not 5 V tolerant. |
| 4 | GPIO23/EQEP1I/LINRXA | bidirectional | General-purpose I/O 23; alternates are eQEP1 index (I/O) and LIN receive (I); inputs are not 5 V tolerant. |
| 5 | GPIO42/COMP1OUT | bidirectional | General-purpose I/O 42 with comparator 1 direct output (O) as alternate; inputs are not 5 V tolerant. |
| 6 | GPIO43/COMP2OUT | bidirectional | General-purpose I/O 43 with comparator 2 direct output (O) as alternate; inputs are not 5 V tolerant. |
| 7 | VDD | power_in | CPU and logic digital supply; 1.8 V nominal, supplied by internal VREG when VREGENZ is low (1.2 µF minimum per VDD pin) or by external 1.71-1.995 V when VREG is disabled. |
| 8 | VSS | power_in | Digital ground. |
| 9 | XRS | bidirectional | Device reset input and watchdog reset output, open-drain with internal pull-up; a 2.2 kΩ to 10 kΩ resistor to VDDIO is recommended and any noise-filter capacitor to VSS should be 100 nF or less. |
| 10 | TRST | input | JTAG test reset with internal pull-down; must be held low during normal operation and needs an external pull-up (about 2.2 kΩ is typical, to be validated for the debug probe). |
| 11 | ADCINA7 | input | ADC group A channel 7 analog input; ADC full scale is 0 V to 3.3 V in internal reference mode and inputs must not exceed VDDA. |
| 12 | ADCINA6/COMP3A/AIO6 | input | ADC group A channel 6 analog input, also comparator 3A input and digital AIO6; AIO function is disabled at reset. |
| 13 | ADCINA5 | input | ADC group A channel 5 analog input (80-pin PN package only); unused ADC inputs should be tied to VSSA. |
| 14 | ADCINA4/COMP2A/AIO4 | input | ADC group A channel 4 analog input, also comparator 2A input and digital AIO4; AIO function is disabled at reset. |
| 15 | ADCINA3 | input | ADC group A channel 3 analog input; unused ADC inputs should be tied to VSSA. |
| 16 | ADCINA2/COMP1A/AIO2 | input | ADC group A channel 2 analog input, also comparator 1A input and digital AIO2; AIO function is disabled at reset. |
| 17 | ADCINA1 | input | ADC group A channel 1 analog input; unused ADC inputs should be tied to VSSA. |
| 18 | ADCINA0 | input | ADC group A channel 0 analog input on a dedicated pin in the PN package; inputs must not exceed VDDA when internal or external reference mode is used. |
| 19 | VREFHI | input | ADC external reference high, used only in ADC external reference mode; must not exceed VDDA. |
| 20 | VDDA | power_in | Analog supply, 2.97 V to 3.63 V (3.3 V nominal); place a 2.2 µF capacitor (typical) near this pin. |
| 21 | VSSA | power_in | Analog ground. |
| 22 | VREFLO | input | ADC external reference low; must be at VSSA-referenced ground in internal reference mode, and VREFLO must be limited to 0.66 V or less in external reference mode. |
| 23 | ADCINB0 | input | ADC group B channel 0 analog input; unused ADC inputs should be tied to VSSA. |
| 24 | ADCINB1 | input | ADC group B channel 1 analog input; unused ADC inputs should be tied to VSSA. |
| 25 | ADCINB2/COMP1B/AIO10 | input | ADC group B channel 2 analog input, also comparator 1B input and digital AIO10; AIO function is disabled at reset. |
| 26 | ADCINB3 | input | ADC group B channel 3 analog input; unused ADC inputs should be tied to VSSA. |
| 27 | ADCINB4/COMP2B/AIO12 | input | ADC group B channel 4 analog input, also comparator 2B input and digital AIO12; AIO function is disabled at reset. |
| 28 | ADCINB5 | input | ADC group B channel 5 analog input (80-pin PN package only); unused ADC inputs should be tied to VSSA. |
| 29 | ADCINB6/COMP3B/AIO14 | input | ADC group B channel 6 analog input, also comparator 3B input and digital AIO14; AIO function is disabled at reset. |
| 30 | ADCINB7 | input | ADC group B channel 7 analog input; unused ADC inputs should be tied to VSSA. |
| 31 | GPIO27/HRCAP2/SPISTEB | bidirectional | General-purpose I/O 27; alternates are high-resolution capture 2 input (I) and SPI-B slave transmit enable (I/O); inputs are not 5 V tolerant. |
| 32 | GPIO31/CANTXA | bidirectional | General-purpose I/O 31; alternate is eCAN-A transmit (O); also used by the serial boot loader; inputs are not 5 V tolerant. |
| 33 | GPIO30/CANRXA | bidirectional | General-purpose I/O 30; alternate is eCAN-A receive (I); also used by the serial boot loader; inputs are not 5 V tolerant. |
| 34 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | General-purpose I/O 29; alternates are SCI-A transmit (O), I2C-A clock (open-drain I/O) and trip-zone 3 input (I); inputs are not 5 V tolerant. |
| 35 | VSS | power_in | Digital ground. |
| 36 | VDDIO | power_in | Digital I/O buffer and flash supply, 2.97 V to 3.63 V (3.3 V nominal); must be powered before or with VDD and each pin needs a decoupling capacitor. |
| 37 | GPIO26/HRCAP1/SPICLKB | bidirectional | General-purpose I/O 26; alternates are high-resolution capture 1 input (I) and SPI-B clock (I/O); inputs are not 5 V tolerant. |
| 38 | TEST2 | unconnected | Reserved for TI test use; must be left unconnected on the board. |
| 39 | GPIO9/EPWM5B/LINTXA/HRCAP1 | bidirectional | General-purpose I/O 9; alternates are ePWM5B output (O), LIN transmit (O) and high-resolution capture 1 input (I); inputs are not 5 V tolerant. |
| 40 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28; alternates are SCI-A receive (I), I2C-A data (open-drain I/O) and trip-zone 2 input (I); inputs are not 5 V tolerant. |
| 41 | GPIO18/SPICLKA/LINTXA/XCLKOUT | bidirectional | General-purpose I/O 18; alternates are SPI-A clock (I/O), LIN transmit (O) and XCLKOUT (O/Z, SYSCLKOUT-derived, reset value SYSCLKOUT/4); inputs are not 5 V tolerant. |
| 42 | GPIO17/SPISOMIA/TZ3 | bidirectional | General-purpose I/O 17; alternates are SPI-A slave-out/master-in (I/O) and trip-zone 3 input (I); inputs are not 5 V tolerant. |
| 43 | GPIO8/EPWM5A/ADCSOCAO | bidirectional | General-purpose I/O 8; alternates are ePWM5A output with HRPWM channel (O) and ADC SOCA output (O); inputs are not 5 V tolerant. |
| 44 | GPIO25/SPISOMIB | bidirectional | General-purpose I/O 25; alternate is SPI-B slave-out/master-in (I/O), available on the PN package only; inputs are not 5 V tolerant. |
| 45 | GPIO44 | bidirectional | General-purpose I/O 44 with no peripheral alternate function listed; inputs are not 5 V tolerant. |
| 46 | GPIO16/SPISIMOA/TZ2 | bidirectional | General-purpose I/O 16; alternates are SPI-A slave-in/master-out (I/O) and trip-zone 2 input (I); inputs are not 5 V tolerant. |
| 47 | GPIO12/TZ1/SCITXDA/SPISIMOB | bidirectional | General-purpose I/O 12; alternates are trip-zone 1 input (I), SCI-A transmit (O) and SPI-B slave-in/master-out (I/O, PN package only); inputs are not 5 V tolerant. |
| 48 | GPIO41/EPWM7B | bidirectional | General-purpose I/O 41; alternate is ePWM7B output (O); inputs are not 5 V tolerant. |
| 49 | GPIO7/EPWM4B/SCIRXDA | bidirectional | General-purpose I/O 7; alternates are ePWM4B output (O) and SCI-A receive (I); inputs are not 5 V tolerant. |
| 50 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6; alternates are ePWM4A output with HRPWM channel (O), external ePWM sync input (I) and external ePWM sync output (O); inputs are not 5 V tolerant. |
| 51 | X2 | output | On-chip crystal oscillator output; must be connected to a crystal or ceramic resonator with X1, and left unconnected if not used. |
| 52 | X1 | input | 1.8 V on-chip crystal oscillator input; must not be driven with 3.3 V levels, and must be tied to GND if the oscillator is not used. |
| 53 | VSS | power_in | Digital ground. |
| 54 | VDD | power_in | CPU and logic digital supply pin; 1.8 V nominal, with 1.2 µF minimum decoupling per VDD pin when the internal VREG is used. |
| 55 | GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 | bidirectional | General-purpose I/O 19; alternates are external oscillator clock input XCLKIN (I), SPI-A slave transmit enable (I/O), LIN receive (I) and ECAP1 (I/O); may glitch during power-up when the on-chip VREG is used. |
| 56 | GPIO39 | bidirectional | General-purpose I/O 39 with no peripheral alternate function listed; inputs are not 5 V tolerant. |
| 57 | GPIO38/TCK/XCLKIN | bidirectional | General-purpose I/O 38; default function is JTAG test clock TCK (I, internal pull-up) and alternate is XCLKIN (I); may glitch during power-up when the on-chip VREG is used. |
| 58 | GPIO37/TDO | tri_state | General-purpose I/O 37; JTAG scan data output TDO (O/Z, 8 mA drive) that cannot be used as GPIO while a JTAG debug probe is connected; may glitch during power-up when the on-chip VREG is used. |
| 59 | GPIO35/TDI | bidirectional | General-purpose I/O 35; JTAG test data input TDI (I, internal pull-up) with GPIO function unavailable during debug; may glitch during power-up when the on-chip VREG is used. |
| 60 | GPIO36/TMS | bidirectional | General-purpose I/O 36; JTAG test mode select TMS (I, internal pull-up) with GPIO function unavailable during debug; may glitch during power-up when the on-chip VREG is used. |
| 61 | GPIO11/EPWM6B/LINRXA/HRCAP2 | bidirectional | General-purpose I/O 11; alternates are ePWM6B output (O), LIN receive (I) and high-resolution capture 2 input (I); inputs are not 5 V tolerant. |
| 62 | GPIO5/EPWM3B/SPISIMOA/ECAP1 | bidirectional | General-purpose I/O 5; alternates are ePWM3B output (O), SPI-A slave-in/master-out (I/O) and ECAP1 (I/O); inputs are not 5 V tolerant. |
| 63 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4; alternate is ePWM3A output with HRPWM channel (O); inputs are not 5 V tolerant. |
| 64 | GPIO40/EPWM7A | bidirectional | General-purpose I/O 40; alternate is ePWM7A output with HRPWM channel (O); inputs are not 5 V tolerant. |
| 65 | GPIO10/EPWM6A/ADCSOCBO | bidirectional | General-purpose I/O 10; alternates are ePWM6A output with HRPWM channel (O) and ADC SOCB output (O); inputs are not 5 V tolerant. |
| 66 | GPIO3/EPWM2B/SPISOMIA/COMP2OUT | bidirectional | General-purpose I/O 3; alternates are ePWM2B output (O), SPI-A slave-out/master-in (I/O) and comparator 2 direct output (O); inputs are not 5 V tolerant. |
| 67 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2; alternate is ePWM2A output with HRPWM channel (O); inputs are not 5 V tolerant. |
| 68 | GPIO1/EPWM1B/COMP1OUT | bidirectional | General-purpose I/O 1; alternates are ePWM1B output (O) and comparator 1 direct output (O); inputs are not 5 V tolerant. |
| 69 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0; alternate is ePWM1A output with HRPWM channel (O); inputs are not 5 V tolerant. |
| 70 | VDDIO | power_in | Digital I/O buffer and flash supply, 2.97 V to 3.63 V (3.3 V nominal); decoupling capacitor required on each pin. |
| 71 | VSS | power_in | Digital ground. |
| 72 | VDD | power_in | CPU and logic digital supply pin; 1.8 V nominal, with 1.2 µF minimum decoupling per VDD pin when the internal VREG is used. |
| 73 | VREGENZ | input | Internal regulator enable with internal pull-down: tie to VSS to enable the 1.8 V VREG, or tie to VDDIO to disable VREG and supply VDD externally. |
| 74 | GPIO34/COMP2OUT/COMP3OUT | bidirectional | General-purpose I/O 34; alternates are comparator 2 direct output (O) and comparator 3 direct output (O); may glitch during power-up when the on-chip VREG is used. |
| 75 | GPIO15/TZ1/LINRXA/SPISTEB | bidirectional | General-purpose I/O 15; alternates are trip-zone 1 input (I), LIN receive (I) and SPI-B slave transmit enable (I/O), PN package only; inputs are not 5 V tolerant. |
| 76 | GPIO13/TZ2/SPISOMIB | bidirectional | General-purpose I/O 13; alternates are trip-zone 2 input (I) and SPI-B slave-out/master-in (I/O), PN package only; inputs are not 5 V tolerant. |
| 77 | GPIO14/TZ3/LINTXA/SPICLKB | bidirectional | General-purpose I/O 14; alternates are trip-zone 3 input (I), LIN transmit (O) and SPI-B clock (I/O), PN package only; inputs are not 5 V tolerant. |
| 78 | GPIO20/EQEP1A/COMP1OUT | bidirectional | General-purpose I/O 20; alternates are eQEP1 input A (I) and comparator 1 direct output (O); inputs are not 5 V tolerant. |
| 79 | GPIO21/EQEP1B/COMP2OUT | bidirectional | General-purpose I/O 21; alternates are eQEP1 input B (I) and comparator 2 direct output (O); inputs are not 5 V tolerant. |
| 80 | GPIO24/ECAP1/SPISIMOB | bidirectional | General-purpose I/O 24; alternates are ECAP1 (I/O) and SPI-B slave-in/master-out (I/O), PN package only; inputs are not 5 V tolerant. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-80(12x12) |
| Category | Embedded Processors & Controllers |
| Pins | 80 |
CAD (KiCad official)
- Symbol:
TMS320F28031PNT - Footprint:
Package_QFP:LQFP-80_12x12mm_P0.5mm - 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
- 3D model files:
tms320f28031pnt-etched.step/tms320f28031pnt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tms320f28031pnt.step/tms320f28031pnt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (176 pp, sha256
cb9ccecfd6b5c484, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).