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ISO7421DR

Public Made by Adom

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TI(德州仪器) Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ISO7421DR

TI(德州仪器) · Digital Isolators · SOIC-8

ISO7421DR from TI(德州仪器), in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC1 power_in Power supply for side 1 (input channels), specified for 3.3-V operation from 3.15 V to 3.45 V (limits from the recommended operating conditions on page 7).
2 OUTA output Output of channel A; recommended output current is -4 mA for high level and 4 mA for low level.
3 INB input Input of channel B with TTL thresholds, requiring VIH of at least 2 V and VIL of at most 0.8 V.
4 GND1 power_in Ground connection for VCC1.
5 GND2 power_in Ground connection for VCC2.
6 OUTB output Output of channel B; recommended output current is -4 mA for high level and 4 mA for low level.
7 INA input Input of channel A with TTL thresholds, requiring VIH of at least 2 V and VIL of at most 0.8 V.
8 VCC2 power_in Power supply for side 2 (output channels), specified for 5-V operation from 4.75 V to 5.25 V (limits from page 7).

Key specifications

Parameter Value
Manufacturer TI(德州仪器)
Package SOIC-8
Category Signal Isolation Devices
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage - 3.3-V operation VCC1, VCC2 3.15 3.3 3.45 V 3.3-V operation 7
Supply voltage - 5-V operation VCC2 4.75 5 5.25 V 5-V operation 7
High-level output current IOH -4 mA 7
Low-level output current IOL 4 mA 7
High-level input voltage VIH 2 5.25 V 7
Low-level input voltage VIL 0 0.8 V 7
Signaling rate 1/tui 0 1 Mbps 7
Input pulse duration tui 1 us 7
Junction temperature TJ -40 136 °C 7
Ambient temperature TA -40 25 105 °C ISO7421 (ISO742x rating, not M grade) 7
Supply voltage VCC -0.5 6 V VCC1, VCC2; peak values referenced to network ground 7
Voltage at IN, OUT VI -0.5 V Max VCC + 0.5 V; must not exceed 6 V 7
Output current IO -15 15 mA 7
Maximum junction temperature TJ(max) 150 °C 7
Storage temperature Tstg -65 150 °C 7
Junction-to-ambient thermal resistance, Low-K board RθJA 212 °C/W Low-K board, D (SOIC) 8 pins 8
Junction-to-ambient thermal resistance, High-K board RθJA 116.6 °C/W High-K board, D (SOIC) 8 pins 8
Junction-to-case (top) thermal resistance RθJC(top) 71.6 °C/W 8
Junction-to-board thermal resistance RθJB 57.3 °C/W 8
High-level output voltage, 5-V output side VOH 4.6 V VCC1 and VCC2 at 5 V ±5%; TA = -40°C to 105°C; IOH = -4 mA; see Figure 6; MIN printed as VCCO, 0.8 8
High-level output voltage, 3.3-V output side VOH 3 V VCC1 and VCC2 at 3.3 V ±5%; TA = -40°C to 105°C; IOH = -4 mA; see Figure 6; MIN printed as VCCO, 0.4 10
High-level output voltage, 5-V output side VOH 5 V VCC1 and VCC2 at 5 V ±5%; TA = -40°C to 105°C; IOH = -20 μA; see Figure 6; MIN printed as VCCO, 0.1 8
High-level output voltage, 3.3-V output side VOH 3.3 V VCC1 and VCC2 at 3.3 V ±5%; TA = -40°C to 105°C; IOH = -20 μA; see Figure 6; MIN printed as VCCO, 0.1 10
Low-level output voltage VOL 0.2 0.4 V IOL = 4 mA; see Figure 6 8
Low-level output voltage VOL 0 0.1 V IOL = 20 μA; see Figure 6 8
High-level input current IIH 10 μA INx at 0 V or VCCI 8
Low-level input current IIL -10 μA INx at 0 V or VCCI 8
Common-mode transient immunity CMTI 25 50 kV/μs VCC1 and VCC2 at 5 V ±5%; VI = VCCI or 0 V; see Figure 8 8
Common-mode transient immunity CMTI 25 40 kV/μs VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5%; VI = VCCI or 0 V; see Figure 8 9
Common-mode transient immunity CMTI 25 40 kV/μs VCC1 and VCC2 at 3.3 V ±5%; VI = VCCI or 0 V; see Figure 8 10
Supply current for VCC1 (ISO7421) ICC1 2 4 mA VCC1 and VCC2 at 5 V ±5%; DC to 1 Mbps; VI = VCCI or 0 V, 15 pF load 8
Supply current for VCC2 (ISO7421) ICC2 2 4 mA VCC1 and VCC2 at 5 V ±5%; DC to 1 Mbps; VI = VCCI or 0 V, 15 pF load 8
Supply current for VCC1 (ISO7421) ICC1 2 4 mA VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5%; DC to 1 Mbps; VI = VCCI or 0 V, 15 pF load 9
Supply current for VCC2 (ISO7421) ICC2 1.5 3.5 mA VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5%; DC to 1 Mbps; VI = VCCI or 0 V, 15 pF load 9
Supply current for VCC1 (ISO7421) ICC1 1.5 3.5 mA VCC1 at 3.3 V ±5%, VCC2 at 5 V ±5%; DC to 1 Mbps; VI = VCCI or 0 V, 15 pF load 9
Supply current for VCC2 (ISO7421) ICC2 2 4 mA VCC1 at 3.3 V ±5%, VCC2 at 5 V ±5%; DC to 1 Mbps; VI = VCCI or 0 V, 15 pF load 9
Supply current for VCC1 (ISO7421) ICC1 1.5 3.5 mA VCC1 and VCC2 at 3.3 V ±5%; DC to 1 Mbps; VI = VCCI or 0 V, 15 pF load 10
Supply current for VCC2 (ISO7421) ICC2 1.5 3.5 mA VCC1 and VCC2 at 3.3 V ±5%; DC to 1 Mbps; VI = VCCI or 0 V, 15 pF load 10
Propagation delay time tPLH, tPHL 9 14 ns VCC1 and VCC2 at 5 V ±5%; TA = -40°C to 105°C; See Figure 6. 10
Pulse width distortion PWD 0.3 3.7 ns VCC1 and VCC2 at 5 V ±5%; /tPHL, tPLH/ 10
Part-to-part skew time tsk(pp) 4.9 ns VCC1 and VCC2 at 5 V ±5% 10
Channel-to-channel output skew time tsk(o) 3.6 ns VCC1 and VCC2 at 5 V ±5% 10
Fail-safe output delay time from input power loss tfs 6 μs VCC1 and VCC2 at 5 V ±5%; See Figure 7. 10
Propagation delay time tPLH, tPHL 10 17 ns VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5%; TA = -40°C to 105°C; See Figure 6. 10
Pulse width distortion PWD 0.5 5.6 ns VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5%; /tPHL, tPLH/ 10
Channel-to-channel output skew time tsk(o) 4 ns VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5% 11
Fail-safe output delay time from input power loss tfs 6 μs VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5%; See Figure 7. 11
Propagation delay time tPLH, tPHL 10 17 ns VCC1 at 3.3 V ±5%, VCC2 at 5 V ±5%; TA = -40°C to 105°C; See Figure 6. 11
Pulse width distortion PWD 0.5 4 ns VCC1 at 3.3 V ±5%, VCC2 at 5 V ±5%; /tPHL, tPLH/ 11
Part-to-part skew time tsk(pp) 8.5 ns VCC1 at 3.3 V ±5%, VCC2 at 5 V ±5% 11
Propagation delay time tPLH, tPHL 12 20 ns VCC1 and VCC2 at 3.3 V ±5%; TA = -40°C to 105°C; See Figure 6. 11
Pulse width distortion PWD 1 5 ns VCC1 and VCC2 at 3.3 V ±5%; /tPHL, tPLH/ 11
Part-to-part skew time tsk(pp) 6.8 ns VCC1 and VCC2 at 3.3 V ±5% 11
Channel-to-channel output skew time tsk(o) 5.5 ns VCC1 and VCC2 at 3.3 V ±5% 11

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC VIORM Maximum working insulation voltage 566 VPK VPR Input-to-output test voltage t = 1 s (100% production), partial discharge 5 pC 1062 VPK 15

CAD (KiCad official)

  • Symbol: ISO7421DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: iso7421dr-etched.step / iso7421dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); iso7421dr.step / iso7421dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TI(德州仪器) datasheet (30 pp, sha256 134345938abaca3b, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF