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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DRV8842MPWPREP

Texas Instruments · Stepper Motor Driver · HTSSOP-28-EP

DRV8842MPWPREP from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CP1	bidirectional	Charge pump flying capacitor pin; connect a 0.01-μF 50-V capacitor between CP1 and CP2.
2	CP2	bidirectional	Charge pump flying capacitor pin; connect a 0.01-μF 50-V capacitor between CP1 and CP2.
3	VCP	bidirectional	High-side gate drive voltage; connect a 0.1-μF 16-V ceramic capacitor and a 1-MΩ resistor to VM.
4	VM	power_in	Motor supply input for bridge A, 8.2 to 45 V; both VM pins must be connected to the same supply and bypassed to GND.
5	OUT1	output	H-bridge output 1 connects to the motor winding; both OUT1 pins must be connected together on the PCB.
6	ISEN	bidirectional	Bridge ground / current-sense pin connects to the current sense resistor; both ISEN pins must be connected together on the PCB.
7	OUT2	output	H-bridge output 2 connects to the motor winding; both OUT2 pins must be connected together on the PCB.
8	OUT2	output	H-bridge output 2 connects to the motor winding; both OUT2 pins must be connected together on the PCB.
9	ISEN	bidirectional	Bridge ground / current-sense pin connects to the current sense resistor; both ISEN pins must be connected together on the PCB.
10	OUT1	output	H-bridge output 1 connects to the motor winding; both OUT1 pins must be connected together on the PCB.
11	VM	power_in	Motor supply input for bridge A, 8.2 to 45 V; both VM pins must be connected to the same supply and bypassed to GND.
12	VREF	power_in	Reference voltage for winding current set, recommended 1 to 3.5 V (accuracy degraded below 1 V); both VREF pins must be connected together on the PCB.
13	VREF	power_in	Reference voltage for winding current set, recommended 1 to 3.5 V (accuracy degraded below 1 V); both VREF pins must be connected together on the PCB.
14	GND	power_in	Device ground.
15	V3P3OUT	power_out	3.3-V regulator output (3.1 to 3.5 V, up to 1 mA load) that can supply VREF; bypass to GND with a 0.47-μF 6.3-V ceramic capacitor.
16	nRESET	input	Active-low reset input that initializes the logic and disables the H-bridge outputs; internal pulldown of approximately 100 kΩ and must be driven high for operation.
17	nSLEEP	input	Logic high enables the device and logic low enters low-power sleep mode; internal pulldown of approximately 100 kΩ and must be driven high for operation.
18	nFAULT	output	Open-drain fault output that is driven low during over-temperature or overcurrent faults; output low voltage is 0.5 V max at 5 mA.
19	DECAY	input	Decay mode select: logic low gives slow decay, open gives mixed decay, logic high gives fast decay; internal pullup of about 130 kΩ and pulldown of about 80 kΩ.
20	IN2	input	Logic input that directly controls the state of OUT2; internal pulldown of approximately 100 kΩ.
21	IN1	input	Logic input that directly controls the state of OUT1; internal pulldown of approximately 100 kΩ.
22	NC	unconnected	Labeled NC (no connection) on the datasheet top view; no function is described for this pin.
23	I0	input	Current set input bit 0 that scales winding current as a percentage of full-scale (I[4:0] sets 0% to 100%); internal pulldown of approximately 100 kΩ.
24	I1	input	Current set input bit 1 that scales winding current as a percentage of full-scale (I[4:0] sets 0% to 100%); internal pulldown of approximately 100 kΩ.
25	I2	input	Current set input bit 2 that scales winding current as a percentage of full-scale (I[4:0] sets 0% to 100%); internal pulldown of approximately 100 kΩ.
26	I3	input	Current set input bit 3 that scales winding current as a percentage of full-scale (I[4:0] sets 0% to 100%); internal pulldown of approximately 100 kΩ.
27	I4	input	Current set input bit 4 that scales winding current as a percentage of full-scale (I[4:0] sets 0% to 100%); internal pulldown of approximately 100 kΩ.
28	GND	power_in	Device ground.
29	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-28-EP
Category	Motor Driver ICs
Pins	29

CAD (KiCad official)

Symbol: DRV8842MPWPREP
Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
3D model files: drv8842mpwprep-etched.step / drv8842mpwprep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8842mpwprep.step / drv8842mpwprep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (25 pp, sha256 2d8387d8c2ec0336, retrieved 2026-10-12, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF