component
XD74LS74
Public Made by Adomby adom
XINLUDA Flip Flops, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownXD74LS74
XINLUDA · Flip Flops · DIP-14
XD74LS74 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLR | input | Active-low asynchronous clear for flip-flop 1; a low level resets the outputs regardless of the other inputs. |
| 2 | 1D | input | Data input of flip-flop 1, transferred to the outputs on the positive-going clock edge when preset and clear are high. |
| 3 | 1CLK | input | Positive-edge-triggered clock input of flip-flop 1. |
| 4 | 1PRE | input | Active-low asynchronous preset for flip-flop 1; a low level sets the outputs regardless of the other inputs. |
| 5 | 1Q | output | True output of flip-flop 1. |
| 6 | 1Q̅ | output | Complementary output of flip-flop 1. |
| 7 | GND | power_in | Ground terminal, the reference for all voltage values. |
| 8 | 2Q̅ | output | Complementary output of flip-flop 2. |
| 9 | 2Q | output | True output of flip-flop 2. |
| 10 | 2PRE | input | Active-low asynchronous preset for flip-flop 2; a low level sets the outputs regardless of the other inputs. |
| 11 | 2CLK | input | Positive-edge-triggered clock input of flip-flop 2. |
| 12 | 2D | input | Data input of flip-flop 2, transferred to the outputs on the positive-going clock edge when preset and clear are high. |
| 13 | 2CLR | input | Active-low asynchronous clear for flip-flop 2; a low level resets the outputs regardless of the other inputs. |
| 14 | VCC | power_in | Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC (absolute maximum) | VCC | 7 | V | See Note 1 (voltage values with respect to network ground terminal) | 3 | ||
| Input voltage VI, 74LS74 | VI | 7 | V | 3 | |||
| Operating free-air temperature range, DIP package | TA | 0 | 70 | C | DIP package | 3 | |
| Storage temperature range | Tstg | -65 | 150 | C | 3 | ||
| Supply voltage VCC | VCC | 4.75 | 5 | 5.25 | V | 4 | |
| High-level input voltage | VIH | 2 | V | 4 | |||
| Low-level input voltage | VIL | 0.8 | V | 4 | |||
| High-level output current | IOH | -0.4 | mA | 4 | |||
| Low-level output current | IOL | 8 | mA | 4 | |||
| Clock frequency | fclock | 0 | 25 | MHz | 4 | ||
| Pulse duration, CLK high | tw | 25 | ns | 4 | |||
| Pulse duration, PRE or CLR low | tw | 25 | ns | 4 | |||
| Setup time before CLK↑, high-level data | tsu | 20 | ns | 4 | |||
| Setup time before CLK↑, low-level data | tsu | 20 | ns | 4 | |||
| Hold time, data after CLK↑ | th | 5 | ns | 4 | |||
| Operating free-air temperature | TA | 0 | 70 | C | 4 | ||
| Input clamp voltage D, CLK, CLR, PRE | VIK | -1.5 | V | VCC = MIN, II = −18 mA | 4 | ||
| High-level output voltage | VOH | 2.7 | 3.4 | V | VCC = MIN, VIH = 2 V, IOH = −0.4mA, VIL = MAX | 4 | |
| Low-level output voltage (first printed row) | VOL | 0.25 | 0.4 | V | VCC = MIN, VIH = 2 V, VIL = MAX, IOL = 8mA | 4 | |
| Low-level output voltage (second printed row) | VOL | 0.35 | 0.5 | V | VCC = MIN, VIH = 2 V, VIL = MAX, IOL = 8mA | 4 | |
| Input current at maximum input voltage, D or CLK | II | 0.1 | mA | VCC = MAX, VI = 7 V | 4 | ||
| Input current at maximum input voltage, CLR or PRE | II | 0.2 | mA | VCC = MAX, VI = 7 V | 4 | ||
| High-level input current, D or CLK | IIH | 20 | A | VCC = MAX, VI = 2.7 V | 4 | ||
| High-level input current, CLR or PRE | IIH | 40 | A | VCC = MAX, VI = 2.7 V | 4 | ||
| Low-level input current, D or CLK | IIL | -0.4 | mA | VCC = MAX, VI = 0.4 V | 4 | ||
| Low-level input current, CLR or PRE | IIL | -0.8 | mA | VCC = MAX, VI = 0.4 V | 4 | ||
| Short-circuit output current | IOS | -20 | -100 | mA | VCC = MAX, See Note 4 | 4 | |
| Supply current (total) | ICC (Totall) | 4 | 8 | mA | VCC = MAX, See Note 2 | 4 | |
| Maximum clock frequency | fmax | 25 | 33 | MHz | CL=15 pF, RL=2kΩ, See Note 3 | 4 | |
| Propagation delay low-to-high, CLR or CLK to Q or Q̄ | tPLH | 13 | 25 | ns | 4 | ||
| Propagation delay high-to-low, CLR or CLK to Q or Q̄ | tPHL | 25 | 40 | ns | 4 |
CAD (KiCad official)
- Symbol:
XD74LS74 - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
xd74ls74-etched.step/xd74ls74-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xd74ls74.step/xd74ls74.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (5 pp, sha256
2a44228615faa701, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).