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OPA211AIDR

Texas Instruments · Precision OpAmps · SOIC-8

OPA211AIDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection. May be left floating or tied to any voltage between V- and V+.
2 -IN input Inverting input of the op-amp. Common-mode input range extends to (V-)+1.5 V and up to (V+)-2 V; input bias current typ ±60 nA.
3 +IN input Non-inverting input of the op-amp. Common-mode input range extends to (V-)+1.5 V and up to (V+)-2 V; input bias current typ ±60 nA.
4 V- power_in Negative supply rail. Operates from -18 V to -2.25 V for split supplies, or 0 V (GND) for single-supply operation up to 36 V total across V+ and V-. Bypass to V+ with 0.1 µF ceramic close to the pins.
5 NC unconnected No internal connection. May be left floating or tied to any voltage between V- and V+.
6 OUT output Rail-to-rail amplifier output. Sources/sinks up to ±30 mA short-circuit; output swings to within ~600 mV of each rail at 10 mA load. Slew rate 27 V/µs.
7 V+ power_in Positive supply rail. Operates from +2.25 V to +18 V for split supplies, or 4.5 V to 36 V single-supply (referenced to V-). Bypass to V- with 0.1 µF ceramic close to the pins. Typical supply current 3.6 mA per channel.
8 Shutdown input Active-high shutdown control. Device enabled when (V-) ≤ V_SHUTDOWN ≤ (V+)-3 V; device disabled when V_SHUTDOWN ≥ (V+)-0.35 V. Reduces supply current when asserted.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Op-amp/Cmp
Pins 8

Ordering variants

  • OPA211AIDR
  • OPA211AIDRAIDGK
  • OPA211AIDRAIDGKT
  • OPA211AIDRAIDGKR
  • OPA211AIDRG
  • OPA211AIDRGT
  • OPA211AIDRGR

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
输入失调电压 (Input offset voltage), OPA211 VOS -125 30 125 μV VS = ±15V 7
输入失调电压温漂 (Offset voltage drift) dVOS/dT -1.5 0.35 1.5 μV/°C VS = ±15V, TA = –40°C to +125°C 7
输入失调电压与电源间的关系 (PSRR) PSRR 0.1 1 μV/V TA = 25°C 7
输入失调电压与电源间的关系 (PSRR) PSRR 3 μV/V TA = –40°C to +125°C 7
输入偏置电流 (Input bias current), OPA211 IB -175 60 175 nA VCM = 0V 7
输入偏置电流 (Input bias current), OPA211 IB -200 200 nA VCM = 0V, TA = –40°C to +125°C 7
输入失调电流 (Input offset current) IOS -100 25 100 nA VCM = 0V 7
输入失调电流 (Input offset current) IOS -150 150 nA VCM = 0V, TA = –40°C to +125°C 7
共模抑制比 (CMRR), VS ≥ ±5V CMRR 114 120 dB VS ≥ ±5V, (V–) + 2V ≤ VCM ≤ (V+) – 2V, TA = –40°C to +125°C 7
共模抑制比 (CMRR), VS < ±5V CMRR 110 120 dB VS < ±5V, (V–) + 2V ≤ VCM ≤ (V+) – 2V, TA = –40°C to +125°C 7
开环电压增益 (Open-loop voltage gain) AOL 114 130 dB (V–) + 0.2V ≤ VO ≤ (V+) – 0.2V, RL = 10kΩ, TA = –40°C to +125°C 8
开环电压增益 (Open-loop voltage gain) AOL 110 114 dB (V–) + 0.6V ≤ VO ≤ (V+) – 0.6V, RL = 600Ω 8
开环电压增益 (Open-loop voltage gain), OPA211 AOL 110 dB (V–) + 0.6V ≤ VO ≤ (V+) – 0.6V, IO ≤ 15mA, TA = –40°C to +125°C 8
开环电压增益 (Open-loop voltage gain), OPA211 AOL 103 dB (V–) + 0.6V ≤ VO ≤ (V+) – 0.6V, 15mA < IO ≤ 30mA, TA = –40°C to +125°C 8
关断电流 (Shutdown current) IQ(SD) 1 20 μA Shutdown (disabled) 8
额定电压 (Supply voltage, ±VS) VS 2.25 18 V Dual supply, ±2.25V to ±18V as printed 9
静态电流 (Quiescent current, per channel) IQ 3.6 4.5 mA IOUT = 0A 9
静态电流 (Quiescent current, per channel) IQ 6 mA IOUT = 0A, TA = –40°C to +125°C 9
额定温度范围 (Rated temperature range) TA -40 125 °C 9
温度范围 (Temperature range, second row as printed) TA -55 150 °C 9
结至环境热阻 (Junction-to-ambient, RθJA), OPA211 D (SOIC) RθJA 122.2 °C/W High-K board 6
结至外壳(顶部)热阻 (RθJC(top)), OPA211 D (SOIC) RθJC(top) 62.5 °C/W 6
结至电路板热阻 (RθJB), OPA211 D (SOIC) RθJB 64.3 °C/W 6
结至顶部特征参数 (ψJT), OPA211 D (SOIC) ψJT 14.2 °C/W 6
结至电路板特征参数 (ψJB), OPA211 D (SOIC) ψJB 63.6 °C/W 6

CAD (KiCad official)

  • Symbol: OPA211AIDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: opa211aidr-etched.step / opa211aidr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); opa211aidr.step / opa211aidr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 2b9cee692757525c, retrieved 2026-08-17, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

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