component
MC74HC175ADR2G
Public Made by Adomby adom
onsemi Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74HC175ADR2G
onsemi · Flip Flops · SOIC-16
MC74HC175ADR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | input | Active-low asynchronous reset input that clears all four flip-flops when a low level is applied, independent of the clock. |
| 2 | Q0 | output | Data output of flip-flop 0, which follows the D0 input on the next positive clock edge. |
| 3 | Q0 | output | Complementary (inverted) output of flip-flop 0, driving CMOS, NMOS or TTL loads (10 LSTTL loads). |
| 4 | D0 | input | Data input of flip-flop 0, transferred to Q0 on the next positive-going clock edge. |
| 5 | D1 | input | Data input of flip-flop 1, transferred to Q1 on the next positive-going clock edge. |
| 6 | Q1 | output | Complementary (inverted) output of flip-flop 1, driving CMOS, NMOS or TTL loads (10 LSTTL loads). |
| 7 | Q1 | output | Data output of flip-flop 1, which follows the D1 input on the next positive clock edge. |
| 8 | GND | power_in | Ground reference pin for the device, with all voltages referenced to GND. |
| 9 | CLOCK | input | Common clock input; data at each D input is latched on the positive-going edge, with minimum pulse width of 80 ns at 2.0 V. |
| 10 | Q2 | output | Data output of flip-flop 2, which follows the D2 input on the next positive clock edge. |
| 11 | Q2 | output | Complementary (inverted) output of flip-flop 2, driving CMOS, NMOS or TTL loads (10 LSTTL loads). |
| 12 | D2 | input | Data input of flip-flop 2, transferred to Q2 on the next positive-going clock edge. |
| 13 | D3 | input | Data input of flip-flop 3, transferred to Q3 on the next positive-going clock edge. |
| 14 | Q3 | output | Complementary (inverted) output of flip-flop 3, driving CMOS, NMOS or TTL loads (10 LSTTL loads). |
| 15 | Q3 | output | Data output of flip-flop 3, which follows the D3 input on the next positive clock edge. |
| 16 | VCC | power_in | Positive supply pin, specified for 2.0 V to 6.0 V with respect to GND (absolute maximum 7.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 | 7 | V | Referenced to GND | 3 | |
| DC Input Voltage | Vin | -0.5 | V | Referenced to GND; max VCC + 0.5 | 3 | ||
| DC Output Voltage | Vout | -0.5 | V | Referenced to GND; max VCC + 0.5 | 3 | ||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | 3 | ||
| DC Output Current, per Pin | Iout | -25 | 25 | mA | 3 | ||
| DC Supply Current, VCC and GND Pins | ICC | -50 | 50 | mA | 3 | ||
| Power Dissipation in Still Air, SOIC Package | PD | 500 | mW | Derating -7 mW/C from 65 to 125C | 3 | ||
| Storage Temperature | Tstg | -65 | 150 | C | 3 | ||
| Lead Temperature | TL | 260 | C | 1 mm from case for 10 seconds | 3 | ||
| DC Supply Voltage | VCC | 2 | 6 | V | Referenced to GND | 3 | |
| DC Input/Output Voltage | Vin, Vout | 0 | V | Referenced to GND; max VCC | 3 | ||
| Operating Temperature | TA | -55 | 125 | C | All package types | 3 | |
| Input Rise and Fall Time | tr, tf | 0 | 1000 | ns | VCC = 2.0 V | 3 | |
| Input Rise and Fall Time | tr, tf | 0 | 600 | ns | VCC = 3.0 V | 3 | |
| Input Rise and Fall Time | tr, tf | 0 | 500 | ns | VCC = 4.5 V | 3 | |
| Input Rise and Fall Time | tr, tf | 0 | 400 | ns | VCC = 6.0 V | 3 | |
| Minimum High-Level Input Voltage | VIH | 1.5 | V | VCC=2.0 V, Vout=0.1 V or VCC-0.1 V, /Iout/<=20 uA, -55 to 125C | 4 | ||
| Minimum High-Level Input Voltage | VIH | 2.1 | V | VCC=3.0 V, Vout=0.1 V or VCC-0.1 V, /Iout/<=20 uA, -55 to 125C | 4 | ||
| Minimum High-Level Input Voltage | VIH | 3.15 | V | VCC=4.5 V, Vout=0.1 V or VCC-0.1 V, /Iout/<=20 uA, -55 to 125C | 4 | ||
| Minimum High-Level Input Voltage | VIH | 4.2 | V | VCC=6.0 V, Vout=0.1 V or VCC-0.1 V, /Iout/<=20 uA, -55 to 125C | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 0.5 | V | VCC=2.0 V, Vout=0.1 V or VCC-0.1 V, /Iout/<=20 uA, -55 to 125C | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 0.9 | V | VCC=3.0 V, Vout=0.1 V or VCC-0.1 V, /Iout/<=20 uA, -55 to 125C | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 1.35 | V | VCC=4.5 V, Vout=0.1 V or VCC-0.1 V, /Iout/<=20 uA, -55 to 125C | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 1.8 | V | VCC=6.0 V, Vout=0.1 V or VCC-0.1 V, /Iout/<=20 uA, -55 to 125C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 1.9 | V | VCC=2.0 V, Vin=VIH or VIL, /Iout/<=20 uA, all temps | 4 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | VCC=4.5 V, Vin=VIH or VIL, /Iout/<=20 uA, all temps | 4 | ||
| Minimum High-Level Output Voltage | VOH | 5.9 | V | VCC=6.0 V, Vin=VIH or VIL, /Iout/<=20 uA, all temps | 4 | ||
| Minimum High-Level Output Voltage | VOH | 2.48 | V | VCC=3.0 V, Vin=VIH or VIL, /Iout/<=2.4 mA, -55 to 25C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 2.2 | V | VCC=3.0 V, Vin=VIH or VIL, /Iout/<=2.4 mA, 125C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 3.98 | V | VCC=4.5 V, Vin=VIH or VIL, /Iout/<=4.0 mA, -55 to 25C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 3.7 | V | VCC=4.5 V, Vin=VIH or VIL, /Iout/<=4.0 mA, 125C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 5.48 | V | VCC=6.0 V, Vin=VIH or VIL, /Iout/<=5.2 mA, -55 to 25C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 5.2 | V | VCC=6.0 V, Vin=VIH or VIL, /Iout/<=5.2 mA, 125C | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | VCC=2.0/4.5/6.0 V, Vin=VIH or VIL, /Iout/<=20 uA, all temps | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0.26 | V | VCC=3.0/4.5/6.0 V, Vin=VIH or VIL, /Iout/<=2.4/4.0/5.2 mA, -55 to 25C | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0.4 | V | VCC=3.0/4.5/6.0 V, Vin=VIH or VIL, /Iout/<=2.4/4.0/5.2 mA, 125C | 4 | ||
| Maximum Input Leakage Current | Iin | -0.1 | 0.1 | µA | Vin = VCC or GND, VCC=6.0 V, -55 to 25C | 4 | |
| Maximum Input Leakage Current | Iin | -1 | 1 | µA | Vin = VCC or GND, VCC=6.0 V, 85C and 125C | 4 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 4 | µA | Vin = VCC or GND, Iout = 0 uA, VCC=6.0 V, -55 to 25C | 4 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 40 | µA | Vin = VCC or GND, Iout = 0 uA, VCC=6.0 V, 85C | 4 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 160 | µA | Vin = VCC or GND, Iout = 0 uA, VCC=6.0 V, 125C | 4 | ||
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 6 | MHz | VCC=2.0 V, -55 to 25C, CL=50 pF | 5 | ||
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 30 | MHz | VCC=4.5 V, -55 to 25C, CL=50 pF | 5 | ||
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 35 | MHz | VCC=6.0 V, -55 to 25C, CL=50 pF | 5 | ||
| Maximum Propagation Delay, Clock to Q or Q̄ | tPLH, tPHL | 26 | ns | VCC=4.5 V, -55 to 25C, CL=50 pF | 5 | ||
| Maximum Propagation Delay, Clock to Q or Q̄ | tPLH, tPHL | 38 | ns | VCC=4.5 V, 125C, CL=50 pF | 5 | ||
| Maximum Propagation Delay, Reset to Q or Q̄ | tPHL | 22 | ns | VCC=4.5 V, -55 to 25C, CL=50 pF | 5 | ||
| Maximum Propagation Delay, Reset to Q or Q̄ | tPHL | 34 | ns | VCC=4.5 V, 125C, CL=50 pF | 5 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 15 | ns | VCC=4.5 V, -55 to 25C, CL=50 pF | 5 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 22 | ns | VCC=4.5 V, 125C, CL=50 pF | 5 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 5 | |||
| Minimum Setup Time, Data to Clock | tsu | 20 | ns | VCC=4.5 V, -55 to 25C | 5 | ||
| Minimum Setup Time, Data to Clock | tsu | 30 | ns | VCC=4.5 V, 125C | 5 | ||
| Minimum Hold Time, Clock to Data | th | 3 | ns | VCC=4.5 V, all temps | 5 | ||
| Minimum Recovery Time, Reset Inactive to Clock | trec | 20 | ns | VCC=4.5 V, -55 to 25C | 5 | ||
| Minimum Pulse Width, Clock | tw | 16 | ns | VCC=4.5 V, -55 to 25C | 5 | ||
| Minimum Pulse Width, Reset | tw | 16 | ns | VCC=4.5 V, -55 to 25C | 5 | ||
| Maximum Input Rise and Fall Times | tr, tf | 500 | ns | VCC=4.5 V, all temps | 5 | ||
| Power Dissipation Capacitance (Per Flip-Flop) | CPD | 35 | pF | Typical @ 25°C, VCC = 5.0 V | 5 |
CAD (KiCad official)
- Symbol:
MC74HC175ADR2G - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
mc74hc175adr2g-etched.step/mc74hc175adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc175adr2g.step/mc74hc175adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (10 pp, sha256
999c30a0b7638338, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).