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README

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MP2918GL-Z

MONOLITHIC POWER SYSTEMS (MPS) · Global Sourcing Parts · QFN-20(3x4)

MP2918GL-Z from MONOLITHIC POWER SYSTEMS (MPS), in a QFN-20(3x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC2 power_in External power supply for the internal VCC1 regulator that disables power from VIN while higher than 4.7V; do not connect a supply greater than 12V.
2 VCC1 power_out Internal bias supply requiring a ≥1µF decoupling capacitor between VCC1 and PGND.
3 SGND power_in Low-noise ground reference that should be connected to the VOUT side of the output capacitors.
4 SS passive Soft-start control input that programs the soft-start period with an external capacitor between SS and SGND.
5 COMP passive Regulation control loop compensation node; connect an R-C network from COMP to SGND.
6 FB input Error amplifier input; an external resistive divider from the output to SGND is compared to the internal 0.8V reference to set the regulation voltage.
7 CCM/AAM input Floating it or connecting it to VCC1 selects CCM, while an external resistor to SGND selects AAM with the AAM voltage no less than 480mV.
8 FREQ passive Frequency set pin; connect a resistor between FREQ and SGND to set the switching frequency.
9 PG output Power good output, open drain.
10 ILIM input Sense voltage limit set with three fixed options (float, VCC1, SGND) that set the nominal sense voltage at maximum output current.
11 SYNCO output Frequency synchronous output providing a 180° out-of-phase clock when the part works in CCM for dual-channel operation.
12 SENSE- input Negative input for current sense; the inductor current limit threshold is determined by the status of ILIM.
13 SENSE+ input Positive input for current sense; the inductor current limit threshold is determined by the status of ILIM.
14 PGND power_in High-current ground reference for the low-side driver and VCC1 regulator, connected directly to the negative terminal of the VCC1 decoupling capacitor.
15 BG output Bottom gate driver output connected to the gate of the synchronous N-channel MOSFET.
16 SW bidirectional Switch node that is the reference for the VBST supply and high-current return for the bootstrapped switch.
17 TG output Top gate drive for the top N-channel MOSFET, powered from the BST capacitor and returning to SW.
18 BST power_in Bootstrap positive supply for the floating high-side driver; connect a bypass capacitor between BST and SW, charged via a diode from VCC1.
19 IN power_in Input supply operating over a 4V to 40V range, needing a ceramic capacitor to prevent large input voltage spikes.
20 EN/SYNC input Enable input with 1.22V threshold and 130mV hysteresis, usable for external UVLO, and an external sync clock applied here makes the internal clock follow.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer MONOLITHIC POWER SYSTEMS (MPS)
Package QFN-20(3x4)
Category Global Sourcing Parts
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN UVLO threshold (rising) INUV_RISING 4 4.5 5 V 4
VIN UVLO threshold (falling) INUV_FALLING 3.2 3.7 3.95 V 4
VIN supply current with VCC2 bias IQ_VCC2 25 40 μA VCC2 = 12V, external bias, VAAM = 5V, VFB = 0.84V, SENSE+ = SENSE- = 0V, no switching 4
VIN supply current without VCC2 bias IQ 750 1000 μA VCC2 = 0V, VFB = 0.84V, VAAM = 5V, SENSE+ = SENSE- = 0V, no switching 4
VIN AAM current IQ_AAM 250 350 μA VCC2 = 0V, VAAM = 0.6V, VFB = 0.84V, SENSE+ = SENSE- = 12V, no switching 4
VIN shutdown current ISHDN 0.5 5 μA VEN = 0V 4
VCC1 regulator output voltage from VIN VCC1_VIN 4.5 5 5.5 V VIN > 6V, load = 0 to 50mA 4
VCC1 regulator load regulation from VIN 1 3 % Load = 0 to 50mA, VCC2 floating or connected to SGND 4
VCC1 regulator load regulation from VCC2 1 3 % Load = 0 to 50mA, VCC2 = 12V 4
VCC2 UVLO threshold (rising) VCC2_RISING 4.3 4.7 4.92 V 4
VCC2 UVLO threshold (falling) VCC2_FALLING 4.05 4.45 4.75 V 4
VCC2 supply current IVCC2 800 1100 μA VAAM = 5V, VFB = 0.84V, SENSE+ = SENSE- = 12V, VCC2 = 12V, no switching 4
VCC2 supply current (AAM) IVCC2 200 300 μA VAAM = 0.6V, VFB = 0.84V, SENSE+ = SENSE- =12V, VCC2 = 12V, no switching 4
Feedback voltage VFB 0.788 0.8 0.812 V 4V ≤ VIN ≤ 40V 4
Feedback current IFB 10 nA VFB = 0.8V 4
Enable threshold (rising) VEN_RISING 1.16 1.22 1.28 V 4
Enable threshold (falling) VEN_FALLING 1.03 1.09 1.15 V 4
Enable input current IEN 2 5 μA VEN/SYNC = 2V 4
Enable turn-off delay tOFF 10 20 40 μs 4
Operating frequency FSW 340 430 520 kHz RFREQ = 45.3kΩ 5
EN/SYNC frequency range FSYNC 100 1000 kHz 5
Current sense common mode voltage range VSENSE+/- 0 25 V 5
Current limit sense voltage VILIMIT 15 25 35 mV ILIM = SGND, VSENSE+ = 3.3V 5
Current limit sense voltage VILIMIT 40 50 60 mV ILIM = VCC1, VSENSE+ = 3.3V 5
Current limit sense voltage VILIMIT 65 75 85 mV ILIM = float, VSENSE+ = 3.3V 5
Input current of sensor ISENSE -70 -45 -20 μA VSENSE+/-(CM) = 0V 5
Input current of sensor ISENSE 80 115 160 μA VSENSE+/-(CM) = 3.3V 5
Input current of sensor ISENSE 105 150 205 μA VSENSE+/-(CM) > 5V 5
Soft-start source current ISS 2 4 6 μA SS = 0.5V 5
Over-voltage threshold VOV 110 115 120 % VFB 5
BG minimum on time tON_MIN_BG 175 250 ns 6
TG maximum duty cycle Dmax 98 99.5 % VFB = 0.7V 6
Power good low VPG_Low 0.1 0.3 V Iload = 4mA 6
PG rising threshold PGVth_RSING 85 90 96.5 % VFB VOUT rising 6
PG rising threshold PGVth_RSING 101 107 112.5 % VFB VOUT falling 6
PG falling threshold PGVth_FALLING 81 87 92.5 % VFB VOUT falling 6
PG falling threshold PGVth_FALLING 105 110 116.5 % VFB VOUT rising 6
Power good leakage IPG_LK 2 μA PG = 5V 6
Input supply voltage VIN 65 V 3
SW voltage SW -0.3 65 V 3
EN/SYNC voltage EN/SYNC 55 V 3
BST - SW 6.5 V 3
Supply voltage VCC1 VCC1 6.5 V 3
External supply voltage VCC2 VCC2 15 V 3
SENSE+/- 28 V 3
Differential sense -0.7 0.7 V SENSE+ to SENSE- 3
All other pins -0.3 6.5 V 3
Continuous power dissipation PD 2.6 W TA = +25°C, QFN-20 (3mmx4mm) 3
Storage temperature -65 175 °C 3
Supply voltage VIN 4 40 V 3
Output voltage VOUT 25 V 3
Supply voltage for VCC2 VCC2 4.7 12 V 3
Operating junction temperature TJ -40 125 °C 3
Thermal resistance junction-ambient θJA 48 °C/W QFN-20 (3mmx4mm) 3
Thermal resistance junction-case θJC 10 °C/W QFN-20 (3mmx4mm) 3

CAD (KiCad official)

  • Symbol: MP2918GL-Z
  • Footprint: Package_DFN_QFN:QFN-20-1EP_3x4mm_P0.5mm_EP1.65x2.65mm
  • 3D model: QFN-20(3x4) (KiCad packages3D, STEP)
  • 3D model files: mp2918gl-z-etched.step / mp2918gl-z-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mp2918gl-z.step / mp2918gl-z.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: MONOLITHIC POWER SYSTEMS (MPS) datasheet (30 pp, sha256 6c8eb0da8f966f5f, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF