TPS2378DDAR from Texas Instruments, in a SO-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Connect to positive PoE input power rail. Bypass with 0.1 µF to VSS. Absolute max 100 V; recommended operating range 0-57 V.
2	DEN	bidirectional	Detection enable. Connect 24.9 kΩ (nom, 23.7-26.3 kΩ or 25 kΩ ±5%) from DEN to VDD for PoE detection signature. Pull to VSS to disable the pass MOSFET. Max sourcing current 1 mA.
3	CLS	output	Classification programming output. Connect a resistor (min 60 Ω) from CLS to VSS to program the PoE classification current (e.g. 63.4 Ω → Class 4 ~40 mA). Max sinking current 65 mA. Do not apply external voltage.
4	VSS	power_in	Negative power rail derived from the PoE source; serves as the local device ground reference. PowerPAD must be tied to this net.
5	RTN	power_out	Drain of the internal PoE pass MOSFET; provides the return path to the downstream DC/DC converter. Absolute max −0.6 to 100 V vs VSS; recommended operating 0-57 V; sinking current up to 0.85 A (1 A typ, 1.2 A max).
6	CDB	output	Active-low, open-drain converter disable output, referenced to RTN. Used to enable/disable the downstream DC/DC converter. Max sinking current 5 mA (2 mA recommended); voltage to RTN 0-57 V.
7	T2P	output	Active-low Type-2 PSE indication, referenced to RTN. Asserts low when a Type-2 PSE is connected or APD is active. Open-drain; max sinking current 5 mA.
8	APD	input	Auxiliary Power Detect input for adapter priority. Raise ≥1.5 V above RTN (threshold ~1.5 V typ, 0.3 V hysteresis) to disable the pass MOSFET and force T2P active. Absolute max −0.3 to 19 V vs RTN; recommended 0-18 V.
PAD	PowerPAD	power_in	Exposed thermal pad on the bottom of the HSOP package. Must be connected to VSS with a large copper fill for heat dissipation (RθJA 45.9 °C/W, RθJC(bot) 6.7 °C/W).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SO-8-EP
Category	Interface
Pins	9

Ordering variants

Same part, different packaging or reel option.

TPS2378DDAR

CAD (KiCad official)

Symbol: TPS2378DDAR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SO-8-EP (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`tps2378ddar.step`	122 KB	You want the bare part, or you mark your own boards.
`tps2378ddar-etched.step`	2.4 MB	You want the part with `TPS2378DDAR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 577 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (34 pp, sha256 e2f91ed8dc5b0495, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF