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CS5464-ISZ

Public Made by Adom

by adom

Cirrus Logic Energy Metering ICs, SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CS5464-ISZ

Cirrus Logic · Energy Metering ICs · SSOP-28-208mil

CS5464-ISZ from Cirrus Logic, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XOUT passive Crystal oscillator output pin, connected to an external quartz crystal (an external clock may instead be supplied to XIN).
2 CPUCLK output Logic-level clock output from the crystal oscillator to drive an external CPU, inverted from XIN by default.
3 VD+ power_in Positive digital supply, 3.135 V to 5.25 V per the recommended operating conditions.
4 DGND power_in Digital ground, the 0 V reference for the digital supply.
5 SCLK bidirectional Serial clock; a Schmitt-trigger input when MODE is low and a driven output when MODE is high.
6 SDO tri_state Serial data output clocked by SCLK; its output drivers are disabled whenever CS is de-asserted.
7 CS bidirectional Chip select that enables the serial interface when MODE is low and is a driven output when MODE is high.
8 MODE input High selects an external E2PROM and low selects an external microcontroller; it has a weak internal pull-down.
9 VIN+ power_in Positive differential voltage input feeding the 10x fixed-gain voltage channel with a full-scale of ±250 mV.
10 VIN- power_in Negative differential voltage input of the voltage channel.
11 VREFOUT output On-chip voltage reference output, nominally 2.5 V referenced to AGND, not recommended for driving external circuits.
12 VREFIN input Voltage reference input requiring a stable 2.5 V, connected to VREFOUT or an external 2.5 V reference.
13 TEST1 passive Factory use only; connect to AGND.
14 TEST2 passive Factory use only; connect to AGND.
15 IIN2- passive Negative differential input of the current channel 2.
16 IIN2+ passive Positive differential input of the current channel 2.
17 AGND power_in Analog ground, the reference for the analog inputs and VREFOUT.
18 VA+ power_in Positive analog supply, 4.75 V to 5.25 V per the recommended operating conditions.
19 IIN1- passive Negative differential input of the current channel 1.
20 IIN1+ passive Positive differential input of the current channel 1.
21 PFMON input Power fail monitor input, fed through a resistive divider from the unregulated supply; its comparator trips around the VREFIN level.
22 E3 output Primarily active-low energy pulse output that can be programmed to output other conditions.
23 RESET input Active-low Schmitt-trigger input that halts all operations and resets the chip when asserted.
24 INT output Active-low interrupt output that indicates an enabled condition has occurred.
25 E1 output Primarily active-low energy pulse output that can be programmed to output other conditions.
26 E2 output Primarily active-low energy pulse output that can be programmed to output other conditions.
27 SDI input Serial data input clocked in by SCLK.
28 XIN input Crystal input for an external quartz crystal, or an external clock input for the system clock.

Key specifications

Parameter Value
Manufacturer Cirrus Logic
Package SSOP-28-208mil
Category Data Converters
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Positive Digital Power Supply VD+ 3.135 5 5.25 V 7
Positive Analog Power Supply VA+ 4.75 5 5.25 V 7
Specified Temperature Range TA -40 85 °C 7
Common Mode Rejection CMRR 80 dB DC, 50, 60 Hz 7
Common Mode + Signal -0.25 V Max printed as VA+ 7
Differential Input Range (Gain = 10) IIN 500 mVP-P Gain = 10 7
Differential Input Range (Gain = 50) IIN 100 mVP-P Gain = 50 7
Total Harmonic Distortion THD 80 94 dB Gain = 50 7
Effective Input Impedance EII 30 k 7
Noise (Referred to Input) NI 22.5 µVrms Gain = 10 7
Noise (Referred to Input) NI 4.5 µVrms Gain = 50 7
Power Supply Current Active State IA+ IA+ 1.5 mA 8
Power Supply Current ID+ ID+ 3.5 mA VA+ = VD+ = 5 V 8
Power Supply Current ID+ ID+ 2.3 mA VA+ = 5 V, VD+ = 3.3 V 8
Power Consumption Active State PC 25 33 mW Active State (VA+ = VD+ = 5 V) 8
Power Consumption Active State PC 15 20 mW Active State (VA+ = 5 V, VD+ = 3.3 V) 8
Power Supply Rejection Ratio Voltage PSRR 48 55 dB 50, 60 Hz, Voltage 8
Power Supply Rejection Ratio Current (Gain = 50x) PSRR 68 75 dB 50, 60 Hz, Current (Gain = 50x) 8
Power Supply Rejection Ratio Current (Gain = 10x) PSRR 60 65 dB 50, 60 Hz, Current (Gain = 10x) 8
PFMON Low-voltage Trigger Threshold PMLO 2.3 2.45 V 8
PFMON High-voltage Power-on Trip Point PMHI 2.55 2.7 V 8
Total Harmonic Distortion (Voltage Inputs) THD 65 75 dB Voltage inputs 8
Noise (Referred to Input) Voltage Inputs NV 140 µVrms 8
Output Voltage VREFOUT 2.4 2.5 2.6 V 9
Load Regulation VR 6 10 mV Maximum recommended output of 1 µA, source or sink 9
Input Voltage Range VREFIN 2.4 2.5 2.6 V 9
Master Clock Frequency DCLK 2.5 4.096 20 MHz Internal Gate Oscillator 10
Master Clock Duty Cycle 40 60 % 10
CPUCLK Duty Cycle 40 60 % 10
Phase Compensation Range -5.4 5.4 ° 60 Hz, OWR = 4000 Hz 10
Full-scale DC Calibration Range (Referred to Input) FSCR 25 100 %FS 10
Low-level Input Voltage (VD = 5 V) VIL 0.8 V All pins except XIN, SCLK and RESET 10
Low-level Input Voltage (VD = 5 V) VIL 1.5 V XIN 10
Low-level Input Voltage (VD = 3.3 V) VIL 0.48 V All pins except XIN, SCLK and RESET 10
Low-level Input Voltage (VD = 3.3 V) VIL 0.3 V XIN 10
Low-level Output Voltage VOL 0.4 V Iout = -5 mA (VD = +5V) 10
Input Leakage Current Iin -10 10 µA Note 16 10
3-state Leakage Current IOZ -10 10 µA 10
Serial Clock Frequency SCLK 2 MHz 11
Serial Clock Pulse Width High t1 200 ns 11
Serial Clock Pulse Width Low t2 200 ns 11
CS Falling to SCLK Rising t3 50 ns 11
Data Set-up Time Prior to SCLK Rising t4 50 ns 11
Data Hold Time After SCLK Rising t5 100 ns 11
CS Falling to SDO Driving t6 20 50 ns 11
SCLK Falling to New Data Bit (hold time) t7 20 50 ns 11
CS Rising to SDO Hi-Z t8 20 50 ns 11
Period tperiod 500 s Note 19 and 20 13
Pulse Width tpw 244 s Note 19 and 20 13
E2 Setup to E1 and/or E3 Falling Edge t4 1.5 s Note 19 and 20 13
E1 Falling Edge to E3 Falling Edge t5 248 s Note 19 and 20 13
Positive Digital Power Supply VD+ -0.3 6 V Notes 21 and 22 13
Positive Analog Power Supply VA+ -0.3 6 V Notes 21 and 22 13
Input Current, Any Pin Except Supplies IIN -10 10 mA Notes 23, 24, 25 13
Output Current, Any Pin Except VREFOUT IOUT 100 mA 13
Power Dissipation PD 500 mW Note 26 13
Analog Input Voltage All Analog Pins VINA -0.3 V Max printed as (VA+) + 0.3 V 13
Ambient Operating Temperature TA -40 85 °C 13
Storage Temperature Tstg -65 150 °C 13

CAD (KiCad official)

  • Symbol: CS5464-ISZ
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
  • 3D model files: cs5464-isz-etched.step / cs5464-isz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs5464-isz.step / cs5464-isz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cirrus Logic datasheet (46 pp, sha256 a6f6b7e7235d37d8, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF