component
PIC12F508-I
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownPIC12F508-I
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · DIP-8
PIC12F508-I from Microchip Tech, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply for logic and I/O pins, specified at 2.0 V to 5.5 V (parameter D001). |
| 2 | GP5/OSC1/CLKIN | bidirectional | Bidirectional I/O pin GP5; also the OSC1 crystal input in XT and LP modes and the CLKIN external clock input (Schmitt trigger) in EXTRC mode. |
| 3 | GP4/OSC2 | bidirectional | Bidirectional I/O pin GP4; serves as the OSC2 crystal output only in XT and LP oscillator modes and is GPIO in other modes. |
| 4 | GP3/MCLR/VPP | input | Input-only pin GP3; when configured as MCLR it is an active-low device Reset with weak pull-up always on, and VPP is the programming voltage input, which must not exceed VDD during normal operation. |
| 5 | GP2/T0CKI | bidirectional | Bidirectional I/O pin GP2; alternate function is T0CKI, the Schmitt-trigger clock input to TMR0. |
| 6 | GP1/ICSPCLK | bidirectional | Bidirectional I/O pin GP1 with weak pull-up and wake-on-change capability; ICSPCLK is the In-Circuit Serial Programming clock (Schmitt-trigger input). |
| 7 | GP0/ICSPDAT | bidirectional | Bidirectional I/O pin GP0 with weak pull-up and wake-on-change capability; ICSPDAT is the In-Circuit Serial Programming data pin. |
| 8 | VSS | power_in | Ground reference for logic and I/O pins. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | DIP-8 |
| Category | Embedded Processors & Controllers |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD Supply Voltage | VDD | 2 | 5.5 | V | See Figure 10-1 | 71 | |
| Input High Voltage, I/O ports with TTL buffer | VIH | 2 | V | 4.5 ≤ VDD ≤ 5.5V | 73 | ||
| Input Leakage Current, I/O ports | IIL | -1 | 1 | µA | Vss ≤ VPIN ≤ VDD, Pin at high-impedance | 73 | |
| Input Leakage Current, GP3/RB3/MCLR (input, pull-up disabled) | IIL | -5 | 5 | µA | Vss ≤ VPIN ≤ VDD | 73 | |
| Input Leakage Current, OSC1 | IIL | -5 | 5 | µA | Vss ≤ VPIN ≤ VDD, XT, HS and LP oscillator configuration | 73 | |
| Capacitive loading, OSC2 pin | CIO | 15 | pF | In XT, HS and LP modes when external clock is used to drive OSC1 | 73 | ||
| Oscillator Frequency, XT mode (CLKIN) | FOSC | 4 | MHz | XT Oscillator mode | 76 | ||
| Oscillator Frequency, EXTRC mode | FOSC | 4 | MHz | EXTRC Oscillator mode | 76 | ||
| External CLKIN Period, LP mode | TOSC | 5 | µs | LP Oscillator mode | 76 | ||
| Oscillator Period, LP mode | TOSC | 5 | µs | LP Oscillator mode | 76 | ||
| Clock in (OSC1) Low or High Time, XT | TosL, TosH | 50 | ns | XT Oscillator | 76 | ||
| Clock in (OSC1) Low or High Time, LP | TosL, TosH | 2 | µs | LP Oscillator | 76 | ||
| Clock in (OSC1) Rise or Fall Time, XT | TosR, TosF | 25 | ns | XT Oscillator | 76 | ||
| Clock in (OSC1) Rise or Fall Time, LP | TosR, TosF | 50 | ns | LP Oscillator | 76 | ||
| Port Output Rise Time | TIOR | 10 | 25 | ns | Design target, not tested (**) | 78 | |
| Port Output Fall Time | TIOF | 10 | 25 | ns | Design target, not tested (**) | 78 | |
| T0CKI High Pulse Width, with prescaler | Tt0H | 10 | ns | With Prescaler | 80 | ||
| T0CKI Low Pulse Width, with prescaler | Tt0L | 10 | ns | With Prescaler | 80 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | 8-Lead Plastic Small Outline (SN), Narrow, 150 mil (SOIC) Foot Angle φ 048048 | 88 |
CAD (KiCad official)
- Symbol:
PIC12F508-I - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files:
pic12f508-i-etched.step/pic12f508-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic12f508-i.step/pic12f508-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (98 pp, sha256
1dac3641a5726f1c, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).