UCC28633DR from Texas Instruments, in a SOIC-7. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VSENSE	input	Sense pin for the flyback transformer bias and sense winding used for output feedback regulation, output OVP, and input voltage sense/UV protection, with absolute maximum range -0.3 V to VDD.
2	SD	input	Latching fault shutdown input pin that may be connected to an external temperature sensor, with absolute maximum range -0.3 V to VDD.
3	CS	input	Current sense input, with recommended input range 0 to 1.0 V and absolute maximum range -0.3 V to 1.5 V.
4	GND	power_in	Ground reference connection for all signals; all voltages are specified with respect to GND.
5	DRV	output	Output drive pin for the external flyback MOSFET, with high-level source resistance of 22 to 35 Ω and low-level sink resistance of 1.2 to 2.5 Ω.
6	VDD	power_in	Bias supply input with absolute maximum of 20 V, to be decoupled with a 1-µF ceramic bypass capacitor connected directly across pins 6-4.
8	HV	power_in	High-voltage connection to the internal start-up current source, with absolute maximum of 700 V and an external 200 kΩ (180 to 220 kΩ) resistor on the HV pin.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-7
Category	Power Management (PMIC)
Pins	7

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Start-up pin voltage HV	HV			700	V		6
Bias supply voltage	VDD			20	V		6
Current sense input voltage	CS	-0.3		1.5	V		6
All other input pins VSENSE	VSENSE	-0.3			V	max is VDD	6
All other input pins SD	SD	-0.3			V	max is VDD	6
Operating junction temperature range	TJ	-40		125	°C		6
Storage temperature	Tstg	-65		125	°C		6
Lead temperature				260	°C		6
CS input	CS	0		1	V		6
All other inputs (except HV, CS)		0			V	max is VDD	6
SD pin external capacitance		0		1	nF		6
External resistor on HV pin, see Figure 15	RHV	180	200	220	kΩ		6
External pull-up resistor on VSENSE pin, see Figure 21	RP	3.8	3.9	4	kΩ		6
Start-up current VDD pin short-circuit charging current	IVDD0	0.6	0.9	1.2	mA	VDD = 0.2 V, VHV = 100 V	8
VDD pin final charging current	IVDD1	1.1	4	7.6	mA	VDD = 11.9 V, VHV = 100 V	8
HV current source leakage current	ILEAK		0.1	0.5	µA	VDD = 18 V, VHV = 100 V HV, current source off, TA = 25°C	8
VDD start-up voltage	VDD(start)	13	14.75	16.5	V	VDD increasing	8
VDD minimum operating voltage after start-up	VDD(stop)	7.3	8	8.5	V	VDD decreasing after start-up	8
VDD start, VDD stop level	VDD(hyst)		6.5		V		8
VDD reset restart level	VDD(reset)	3.5	5	6.5	V		8
VDD over-voltage protection level	VDD(ovp)	16.5	17.5	18.3	V	VDD increasing after start-up, UCC28630, UCC28631, UCC28632, UCC28633	8
Supply current during normal operation	IDD(run)	6	9	13	mA	VSENSE = 0.45 V, CS = 0 V; CLOAD = 700 pF on DRV	8
Supply current during sleep mode, between switching pulses	IDD(sleep)		90	110	µA	VSENSE = 8.0 V, VCS = 1.0 V, light-load mode at 200 Hz, TA = 25°C	8
Maximum switching frequency	fSW(max)	110	120	130	kHz	VSENSE = 0.45 V, VCS = 0 V	8
Minimum switching frequency	fSW(min)	0.18	0.2	0.22	kHz	VSENSE = 8.0 V, VCS = 1.0 V, light-load mode	8
Maximum Duty Cycle	DMAX			70	%	VSENSE = 0.45 V, VCS = 0 V	8
Minimum On time	tON(min)	550	600	650	ns	VSENSE = 8.0 V, VCS = 1.0 V, light-load mode	8
Frequency dither range	fSW(dith)	-6.7		6.7	%	Except UCC28632	8
Dither repetition period	tDITH		6		ms	Except UCC28632	8
Internal pull-up current source	IPULLUP	185	210	235	µA		8
Fault ok level (rising), UCC28633	VTRIP(rise)	3.2	3.5	3.8	V	UCC28630, UCC28631, UCC28632, UCC28633	8
Fault trip level (falling)	VTRIP(fall)	1.7	2	2.3	V		8
VTRIP hysteresis	VTRIP(hyst)		1.5		V		8
Wake delay time	tWAKE		10		µs	Delay to first DRV pulse	8
Internal output voltage sense reference level	VOUT(ref)	7.425	7.5	7.575	V	Required positive voltage at VSENSE pin during off-time (at 25°C)	9
Vsense sample delay for VOUT	tOUT(smp)		1.7		µs	Measured w.r.t. DRV falling edge	9
Peak CS pin voltage level (maximum)	VCS(max)		800		mV	At maximum modulator demand	9
Peak CS pin voltage level (minimum)	VCS(min)		172		mV	At minimum modulator demand	9
Slope compensation ramp	VSLOPE		30		mV/µs		9
Thermal protection shutdown temperature	TEMPTRIP		125		°C	Default internal setting, latch-off protection	9
Thermal protection hysteresis	TEMPHYST		10		°C		9
High level source resistance	ROH	22	35		Ω	IOH = 100 mA	9
Low level sink resistance	ROL	1.2	2.5		Ω	IOL = -100 mA	9
Junction-to-ambient thermal resistance	θJA		128.5		°C/W	UCC28633 D 7 pins	7
Junction-to-case (top) thermal resistance	θJCtop		57.3		°C/W	UCC28633 D 7 pins	7
Junction-to-board thermal resistance	θJB		83.4		°C/W	UCC28633 D 7 pins	7
Junction-to-top characterization parameter	ψJT		12.3		°C/W	UCC28633 D 7 pins	7
Junction-to-board characterization parameter	ψJB		82.1		°C/W	UCC28633 D 7 pins	7

CAD (KiCad official)

Symbol: UCC28633DR
Footprint: Package_SO:SOIC-8-N7_3.9x4.9mm_P1.27mm
3D model: SOIC-7 (KiCad packages3D, STEP)
3D model files: ucc28633dr-etched.step / ucc28633dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc28633dr.step / ucc28633dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (86 pp, sha256 ed73cdcfa09610b8, retrieved 2026-11-06, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

UCC28633DR

Verified UCC28633DR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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