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CD4027BM

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HGSEMI Flip Flops, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

markdown

CD4027BM

HGSEMI · Flip Flops · SOP-16

CD4027BM from HGSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 2Q output Non-inverting output of JK flip-flop 2, and the datasheet states the outputs are buffered to ease system design.
2 ~{2Q} output Inverting output of JK flip-flop 2.
3 2CP input Rising-edge-triggered clock input for flip-flop 2, with an internal Schmitt-trigger structure; data is transferred to the outputs on the rising edge.
4 2CD input Active-high asynchronous clear input for flip-flop 2, which operates independently of the J, K and CP states.
5 2K input K data input of flip-flop 2; the datasheet requires unused inputs to be tied to VDD, VSS or another input and not left floating.
6 2J input J data input of flip-flop 2; the datasheet requires unused inputs to be tied to VDD, VSS or another input and not left floating.
7 2SD input Active-high asynchronous set input for flip-flop 2, which operates independently of the J, K and CP states.
8 VSS power_in Ground reference, VSS = 0 V for the electrical characteristics.
9 1SD input Active-high asynchronous set input for flip-flop 1, which operates independently of the J, K and CP states.
10 1J input J data input of flip-flop 1; the datasheet requires unused inputs to be tied to VDD, VSS or another input and not left floating.
11 1K input K data input of flip-flop 1; the datasheet requires unused inputs to be tied to VDD, VSS or another input and not left floating.
12 1CD input Active-high asynchronous clear input for flip-flop 1, which operates independently of the J, K and CP states.
13 1CP input Rising-edge-triggered clock input for flip-flop 1, with an internal Schmitt-trigger structure; data is transferred to the outputs on the rising edge.
14 ~{1Q} output Inverting output of JK flip-flop 1.
15 1Q output Non-inverting output of JK flip-flop 1, and the datasheet states the outputs are buffered to ease system design.
16 VDD power_in Supply voltage; the recommended operating range is 3 V to 15 V.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 18 V 3
Input clamp current IIK -10 10 mA VI < 0.5 V 或VI > VDD + 0.5 V 3
Input voltage VI -0.5 V 3
Output clamp current IOK -10 10 mA VO < 0.5 V 或VO > VDD + 0.5 V 3
Input/output current II/O -10 10 mA 3
Supply current IDD 50 mA 3
Power dissipation SOP16 PD 500 mW Tamb=-40℃ ～ +125,见注 3
Operating ambient temperature Tamb -40 85 ℃ 3
Storage temperature Tstg -65 150 ℃ 3
Soldering temperature SOP TL 250 ℃ 10 秒 3
Supply voltage (recommended) VDD 3 15 V 4
Input voltage (recommended) VI 0 V 4
Operating ambient temperature (recommended) Tamb -40 85 ℃ 4
Rise/fall input transition rate t/V 3.75 ns/V VDD=5V 4
Rise/fall input transition rate t/V 0.5 ns/V VDD=10V 4
Rise/fall input transition rate t/V 0.08 ns/V VDD=15V 4
High-level input voltage VIH 3.5 V VDD=5V, IO< 1 A 4
High-level input voltage VIH 7 V VDD=10V, IO< 1 A 4
High-level input voltage VIH 11 V VDD=15V, IO< 1 A 4
Low-level input voltage VIL 1.5 V VDD=5V, IO< 1 A 4
Low-level input voltage VIL 3 V VDD=10V, IO< 1 A 4
Low-level input voltage VIL 4 V VDD=15V, IO< 1 A 4
High-level output voltage VOH 4.95 V VDD=5V, IO< 1 A 4
High-level output voltage VOH 9.95 V VDD=10V, IO< 1 A 4
High-level output voltage VOH 14.95 V VDD=15V, IO< 1 A 4
Low-level output voltage VOL 0.05 V VDD=5V, IO< 1 A 4
Input leakage current II -0.3 0.3 A VDD=15V 4
Input capacitance CI 7.5 pF 4
High-level output current IOH -1.7 mA VO = 2.5, VDD=5V, Tamb=-40℃ 4
High-level output current IOH -1.4 mA VO = 2.5, VDD=5V, Tamb=+25℃ 4
High-level output current IOH -1.1 mA VO = 2.5, VDD=5V, Tamb=+80℃ 4
High-level output current IOH -0.52 mA VO = 4.6V, VDD=5V, Tamb=-40℃ 4
High-level output current IOH -0.44 mA VO = 4.6V, VDD=5V, Tamb=+25℃ 4
High-level output current IOH -0.36 mA VO = 4.6V, VDD=5V, Tamb=+80℃ 4
High-level output current IOH -1.3 mA VO = 9.5V, VDD=10V, Tamb=-40℃ 4
High-level output current IOH -0.9 mA VO = 9.5V, VDD=10V, Tamb=+80℃ 4
High-level output current IOH -3.6 mA VO = 13.5 V, VDD=15V, Tamb=-40℃ 4
High-level output current IOH -3 mA VO = 13.5 V, VDD=15V, Tamb=+25℃ 4
High-level output current IOH -2.4 mA VO = 13.5 V, VDD=15V, Tamb=+80℃ 4
Supply current IDD 4 A IO = 0 A, VDD=5V, Tamb=-40℃ 4
Supply current IDD 30 A IO = 0 A, VDD=5V, Tamb=+80℃ 4
Supply current IDD 8 A IO = 0 A, VDD=10V, Tamb=-40℃ 4
Supply current IDD 60 A IO = 0 A, VDD=10V, Tamb=+80℃ 4
Supply current IDD 16 A IO = 0 A, VDD=15V, Tamb=-40℃ 4
Supply current IDD 120 A IO = 0 A, VDD=15V, Tamb=+80℃ 4
High-to-low propagation delay CP->Q, Q tPHL 105 210 ns VDD=5V, 见图 4 5
High-to-low propagation delay CP->Q, Q tPHL 40 80 ns VDD=10V, 见图 4 5
High-to-low propagation delay CP->Q, Q tPHL 30 60 ns VDD=15V, 见图 4 5
Low-to-high propagation delay CP->Q, Q tPLH 85 170 ns VDD=5V, 见图 4 5
Low-to-high propagation delay CP->Q, Q tPLH 35 70 ns VDD=10V, 见图 4 5
Low-to-high propagation delay CP->Q, Q tPLH 30 60 ns VDD=15V, 见图 4 5
Transition time tt 60 120 ns VDD=5V, 见图 4 5
Transition time tt 30 60 ns VDD=10V, 见图 4 5
Transition time tt 20 40 ns VDD=15V, 见图 4 5

CAD (KiCad official)

  • Symbol: CD4027BM
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4027bm-etched.step / cd4027bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4027bm.step / cd4027bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (9 pp, sha256 5e56b120ed3ee897, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF