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HCPL-091J-500E
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Broadcom AVAGO Digital Isolators, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownHCPL-091J-500E
Broadcom AVAGO · Digital Isolators · SO-16
HCPL-091J-500E from Broadcom AVAGO, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Power supply 1 for the input side, with a recommended operating supply of 3.0 V to 5.5 V and a low ESR 47 nF ceramic decoupling capacitor placed as close as possible to the pin. |
| 2 | GND1 | power_in | Power supply ground 1 for the input side; ground planes for GND1 and GND2 are highly recommended for data rates above 10 Mb/s. |
| 3 | IN1 | input | Logic input signal for channel 1, with logic high input VIH of 2.4 V minimum up to VDD1 and logic low input VIL of 0 V to 0.8 V. |
| 4 | IN2 | input | Logic input signal for channel 2, with logic high input VIH of 2.4 V minimum up to VDD1 and logic low input VIL of 0 V to 0.8 V. |
| 5 | OUT3 | output | Logic output signal for channel 3, with a maximum output current drive of 10 mA. |
| 6 | OUT4 | output | Logic output signal for channel 4, with a maximum output current drive of 10 mA. |
| 7 | NC | unconnected | Not connected. |
| 8 | GND1 | power_in | Power supply ground 1 for the input side; ground planes for GND1 and GND2 are highly recommended for data rates above 10 Mb/s. |
| 9 | GND2 | power_in | Power supply ground 2 for the output side; ground planes for GND1 and GND2 are highly recommended for data rates above 10 Mb/s. |
| 10 | NC | unconnected | Not connected. |
| 11 | IN4 | input | Logic input signal for channel 4, with logic high input VIH of 2.4 V minimum up to VDD1 and logic low input VIL of 0 V to 0.8 V. |
| 12 | IN3 | input | Logic input signal for channel 3, with logic high input VIH of 2.4 V minimum up to VDD1 and logic low input VIL of 0 V to 0.8 V. |
| 13 | OUT2 | output | Logic output signal for channel 2, with a maximum output current drive of 10 mA. |
| 14 | OUT1 | output | Logic output signal for channel 1, with a maximum output current drive of 10 mA. |
| 15 | GND2 | power_in | Power supply ground 2 for the output side; ground planes for GND1 and GND2 are highly recommended for data rates above 10 Mb/s. |
| 16 | VDD2 | power_in | Power supply 2 for the output side, with a recommended operating supply of 3.0 V to 5.5 V and a low ESR 47 nF ceramic decoupling capacitor placed as close as possible to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Broadcom AVAGO |
| Package | SO-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 3.3V operation: Quiescent Supply Current 1 (HCPL-901J/-091J) | IDD1 | 3.3 | 4 | mA | VIN = 0V | 11 | |
| 3.3V operation: Quiescent Supply Current 2 (HCPL-901J/-091J) | IDD2 | 3.3 | 4 | mA | VIN = 0V | 11 | |
| 3.3V operation: Logic Input Current | IIN | -10 | 10 | µA | 11 | ||
| 3.3V operation: Maximum Data Rate | 100 | 110 | MBd | CL = 15 pF | 11 | ||
| 3.3V operation: Clock Frequency | fmax | 50 | MHz | 11 | |||
| 3.3V operation: Propagation Delay Time to Logic Low Output | tPHL | 12 | 18 | ns | 11 | ||
| 3.3V operation: Propagation Delay Time to Logic High Output | tPLH | 12 | 18 | ns | 11 | ||
| 3.3V operation: Pulse Width | tPW | 10 | ns | 11 | |||
| 3.3V operation: Pulse Width Distortion | /PWD/ | 2 | 3 | ns | 11 | ||
| 3.3V operation: Propagation Delay Skew | tPSK | 4 | 6 | ns | 11 | ||
| 3.3V operation: Output Rise Time (10% to 90%) | tR | 2 | 4 | ns | 11 | ||
| 3.3V operation: Output Fall Time (10% to 90%) | tF | 2 | 4 | ns | 11 | ||
| 3.3V operation: Channel-to-Channel Skew (Dual and Quad Channels) | tCSK | 2 | 3 | ns | 11 | ||
| 3.3V operation: Logic Low Output Voltage (first row) | VOL | 0 | 0.1 | V | IOUT = 20 µA, VIN = VIL | 11 | |
| 3.3V operation: Logic Low Output Voltage (second row) | VOL | 0.5 | 0.8 | V | IOUT = 4 mA, VIN = VIL | 11 | |
| 5V operation: Quiescent Supply Current 1 (HCPL-901J/-091J) | IDD1 | 5 | 6 | mA | VIN = 0V | 12 | |
| 5V operation: Quiescent Supply Current 2 (HCPL-901J/-091J) | IDD2 | 5 | 6 | mA | VIN = 0V | 12 | |
| 5V operation: Logic Input Current | IIN | -10 | 10 | µA | 12 | ||
| 5V operation: Common Mode Transient Immunity (Output Logic High or Logic Low) | /CMH/, /CML/ | 15 | 18 | kV/µs | Vcm = 1000V | 12 | |
| 5V operation: Logic Low Output Voltage (first row) | VOL | 0 | 0.1 | V | IOUT = 20 µA, VIN = VIL | 12 | |
| 5V operation: Logic Low Output Voltage (second row) | VOL | 0.5 | 0.8 | V | IOUT = 4 mA, VIN = VIL | 12 | |
| Absolute max: Storage Temperature | TS | -55 | 150 | °C | 10 | ||
| Absolute max: Ambient Operating Temperature | TA | -55 | 125 | °C | Device not damaged; performance not guaranteed | 10 | |
| Absolute max: Supply Voltage | VDD1, VDD2 | -0.5 | 7 | V | 10 | ||
| Absolute max: Input Voltage (upper limit printed as VDD1 + 0.5) | VIN | -0.5 | V | 10 | |||
| Absolute max: Output Voltage (upper limit printed as VDD2 + 0.5) | VOUT | -0.5 | V | 10 | |||
| Absolute max: Output Current Drive | IOUT | 10 | mA | 10 | |||
| Absolute max: Lead Solder Temperature | 260 | °C | 10 s | 10 | |||
| Absolute max: ESD | 2 | kV | Human Body Model | 10 | |||
| Recommended: Ambient Operating Temperature | TA | -40 | 100 | °C | 10 | ||
| Recommended: Supply Voltage | VDD1, VDD2 | 3 | 5.5 | V | 10 | ||
| Recommended: Logic High Input Voltage (upper limit printed as VDD1) | VIH | 2.4 | V | 10 | |||
| Recommended: Logic Low Input Voltage | VIL | 0 | 0.8 | V | 10 | ||
| Recommended: Input Signal Rise and Fall Times | tIR, tIF | 1 | μs | 10 | |||
| Thermal Resistance, 16-Pin SOIC Narrow Body (junction to thermocouple) | θJCT | 41 | °C/W | Thermocouple located at center underside of package | 9 | ||
| Package Power Dissipation, 16-Pin SOIC Narrow Body | PPD | 150 | mW | 9 |
CAD (KiCad official)
- Symbol:
HCPL-091J-500E - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files:
hcpl-091j-500e-etched.step/hcpl-091j-500e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hcpl-091j-500e.step/hcpl-091j-500e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Broadcom AVAGO datasheet (18 pp, sha256
ef8c0b52d535c2c5, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).