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LS7366R-S

Public Made by Adom

by adom

LSI CSI Counters, Dividers, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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LS7366R-S

LSI CSI · Counters, Dividers · SOIC-14

LS7366R-S from LSI CSI, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 fCKO output Crystal oscillator output; a crystal connected between fCKi and fCKO generates the basic filter clock for the A, B and INDEX/ inputs in quadrature count mode.
2 fCKi input Filter clock input that accepts a crystal or an external clock, divided by 2 when MDR0 bit 7 = 1 and by 1 when it is 0, and must satisfy the filter-frequency condition relative to the maximum quadrature clock frequency fQA; in non-quadrature mode it is unused and should be tied to a stable logic state.
3 VSS power_in Ground reference; all voltages on the device are referenced to VSS.
4 SS/ input Active-low slave select; a high-to-low transition selects the device for serial transfer and a low-to-high transition ends the transfer and forces MISO to high impedance.
5 SCK input Serial shift clock supplied by the host processor (slave mode only) that synchronizes MOSI and MISO data transfer.
6 MISO tri_state Serial data output that shifts data out MSB first on the trailing (low) SCK edges and goes to high impedance when SS/ is high, allowing wire-OR connection of multiple slaves.
7 MOSI input Serial data input (RXD) that receives MSB-first data from the host processor on the leading (high) SCK edges.
8 LFLAG/ output Open-drain latched flag output for carry, borrow, compare and index conditions that goes low when active and returns to high impedance only when the status register STR is cleared.
9 DFLAG/ output Push-pull instantaneous flag output that dynamically switches low with carry, borrow, compare and index conditions.
10 INDEX/ input Programmable index input that can load CNTR from DTR, reset CNTR, load OTR from CNTR, or be masked; in quadrature mode it operates synchronously or asynchronously as set in MDR0.
11 B input Quadrature clock B input that is filtered and decoded for direction in quadrature mode, and acts as the direction input in non-quadrature mode (high enables up count).
12 A input Quadrature clock A input that is filtered and decoded for count clocks in quadrature mode, and acts as the count input in non-quadrature mode.
13 CNT_EN input Count enable input with an internal pull-up; counting is enabled when high and disabled when low.
14 VDD power_in Positive supply input; the device operates from 3 V to 5.5 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer LSI CSI
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage (absolute maximum) VDD 7 V All voltages referenced to VSS 4
Operating Temperature TA -25 80 °C 4
Storage Temperature TSTG 150 °C 4
Supply Voltage VDD 3 5.5 V 5
Supply Current IDD 300 400 450 µA VDD = 3.0V 5
Supply Current IDD 700 800 950 µA VDD = 5.0V 5
fCKi Logic High Input Voltage VCH 2.3 V VDD = 3.0V 5
fCKi Logic High Input Voltage VCH 3.7 V VDD = 5.0V 5
fCKi Logic Low Input Voltage VCL 0.7 V VDD = 3.0V 5
fCKi Logic Low Input Voltage VCL 1.3 V VDD = 5.0 5
All Other Inputs Logic High Voltage VAH 2.1 V VDD = 3.0V 5
All Other Inputs Logic High Voltage VAH 3.5 V VDD = 5.0V 5
All Other Inputs Logic Low Voltage VAL 0.5 V VDD = 3.0V 5
All Other Inputs Logic Low Voltage VAL 1 V VDD = 5.0V 5
CNT_EN Low Input Current IIEL 3 5 µA VAL = 0.7V, VDD = 3.0V 5
CNT_EN Low Input Current IIEL 10 15 µA VAL = 1.2V, VDD = 5.0V 5
CNT_EN High Input Current IIEH 1 3 µA VAH = 1.9V, VDD = 3.0V 5
CNT_EN High Input Current IIEH 6 9 µA VAH = 3.2V, VDD = 5.0V 5
LFLAG, DFLAG Sink Current IOFL -1.3 -2 mA VOUT = 0.5V, VDD = 3.0V 5
LFLAG, DFLAG Sink Current IOFL -3.2 -4 mA VOUT = 0.5V, VDD = 5.0V 5
DFLAG Source Current IOFH 1 1.8 mA VOUT = 2.5V, VDD = 3.0V 5
DFLAG Source Current IOFH 2.8 3.6 mA VOUT = 4.5V, VDD = 5.0V 5
fCKO Sink Current IOCL -1.3 -2 mA VOUT = 0.5V, VDD = 3.0V 5
fCKO Sink Current IOCL -3.2 -4 mA VOUT = 0.5V, VDD = 5.0V 5
fCKO Source Current IOCH 1.3 2 mA VOUT = 2.5V, VDD = 3.0V 5
fCKO Source Current IOCH 3.2 4 mA VOUT = 4.5V, VDD = 5.0V 5
TXD/MISO Sink Current IOML -1.5 -2.4 mA VOUT = 0.5V, VDD = 3.0V 5
TXD/MISO Sink Current IOML -3.8 -4.8 mA VOUT = 0.5V, VDD = 5.0V 5
TXD/MISO Source Current IOMH 1.5 2.4 mA VOUT = 2.5V, VDD = 3.0V 5
TXD/MISO Source Current IOMH 3.8 4.8 mA VOUT = 4.5V, VDD = 5.0V 5
SCK High Pulse Width tCH 100 ns VDD = 5V ±10%; TA = -25°C to +85°C 5
SCK Low Pulse Width tCL 100 ns VDD = 5V ±10%; TA = -25°C to +85°C 5
SS/ Set Up Time tCSL 100 ns VDD = 5V ±10%; TA = -25°C to +85°C 5
SS/ Hold Time tCSH 100 ns VDD = 5V ±10%; TA = -25°C to +85°C 5
Inter Command SS/ High Time tCSI 100 ns VDD = 5V ±10%; TA = -25°C to +85°C 5
fCKI High Pulse Width t1 12 ns VDD = 5V ±10% 5
fCKI Pulse Width t2 12 ns VDD = 5V ±10% 5
fCKI Frequency fFCK 40 MHz VDD = 5V ±10% 5
Effective Filter Clock Period t3 25 ns VDD = 5V ±10%; t3 = t1+t2, MDR0 <7> = 0 5
Effective Filter Clock Period t3 50 ns VDD = 5V ±10%; t3 = 2(t1+t2), MDR0 <7> = 1 5
Effective Filter Clock Frequency fF 40 MHz VDD = 5V ±10%; fF = 1/t3 5
Quadrature Separation t4 26 ns VDD = 5V ±10%; t4 > t3 5
Quadrature Clock Pulse Width t5 52 ns VDD = 5V ±10%; t5 2t3 5
Quadrature Clock Frequency fQA, fQB 9.6 MHz VDD = 5V ±10%; fQA = fQB < 1/4t3 5
x1/x2/x4 Count Clock Pulse Width tQ2 12 ns VDD = 5V ±10%; tQ2 = (t3)/2 5
Index Input Pulse Width tid 32 ns VDD = 5V ±10%; tid > t4 5
Index Set Up Time tis 5 ns VDD = 5V ±10% 5
Index Hold Time tih 5 ns VDD = 5V ±10% 5
DFLAG/ Output Width tfw 26 ns VDD = 5V ±10%; tfw = t4 5
Clock A High Pulse Width (non-quadrature) t6 12 ns VDD = 5V ±10% 6
Clock A Low Pulse Width (non-quadrature) t7 12 ns VDD = 5V ±10% 6
Direction Input B Set-up Time t8S 12 ns VDD = 5V ±10% 6
Direction Input B Hold Time t8H 10 ns VDD = 5V ±10% 6
CNT_EN Set-up Time t9S 12 ns VDD = 5V ±10% 6
CNT_EN Hold Time t9H 12 ns VDD = 5V ±10% 6
Clock Frequency (non-Mod-N) fA 40 MHz VDD = 5V ±10%; fA = (1/(t6 + t7)) 6
Clock to DFLAG/ or LFLAG/ Delay t10 20 ns VDD = 5V ±10% 6
DFLAG/ Output Width (non-quadrature) t11 12 ns VDD = 5V ±10%; t10 = t7 6

CAD (KiCad official)

  • Symbol: LS7366R-S
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: ls7366r-s-etched.step / ls7366r-s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ls7366r-s.step / ls7366r-s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LSI CSI datasheet (17 pp, sha256 51b1ffc0846b8ad0, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF