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UC2625MDWREP

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Texas Instruments Brushless DC (BLDC) Motor Driver, SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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UC2625MDWREP

Texas Instruments · Brushless DC (BLDC) Motor Driver · SOIC-28-300mil

UC2625MDWREP from Texas Instruments, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 E/A OUT output Error amplifier output, unity-gain compensated, with an output range of 0.25 V to 3.50 V; when the error amplifier is biased off it appears as a resistor to ground.
2 VREF power_out Regulated 5 V reference for Hall-effect sensors and speed control circuitry, which must be bypassed with at least 0.1 µF to ground; the absolute maximum output current is −50 mA continuous.
3 ISENSE passive Current-sense amplifier output node (ISENSE = 2.5 V + 2 ×
4 ISENSE1 input Current-sense amplifier input, interchangeable with ISENSE2, whose differential signal can reach ±0.5 V before saturation with an input range of −1 V to 2 V.
5 ISENSE2 input Current-sense amplifier input, interchangeable with ISENSE1, whose differential signal can reach ±0.5 V before saturation with an input range of −1 V to 2 V.
6 DIR input Direction input that is loaded into the direction latch and then the two-bit shift register; direction changes are inhibited when SPEED-IN is above 250 mV.
7 SPEED-IN input Speed input that keeps the direction latch transparent only while below 250 mV, and which can be filtered from TACH-OUT.
8 H1 input Hall position sensor input with hysteresis comparator and pullup, with low threshold 0.8-1.25 V and high threshold 1.6-2.0 V, and rise and fall times that must be shorter than 20 µs.
9 H2 input Hall position sensor input with hysteresis comparator and pullup, with low threshold 0.8-1.25 V and high threshold 1.6-2.0 V, and rise and fall times that must be shorter than 20 µs.
10 H3 input Hall position sensor input with hysteresis comparator and pullup, with low threshold 0.8-1.25 V and high threshold 1.6-2.0 V, and rise and fall times that must be shorter than 20 µs.
11 PWR VCC power_in Supply pin carrying the current sourced by the PD outputs, which can be current-limited with a resistor when driving Darlington bases.
12 PDC output Totem-pole low-side driver for N-channel MOSFETs or Darlingtons, active high, with peak current up to 0.5 A.
13 PDB output Totem-pole low-side driver for N-channel MOSFETs or Darlingtons, active high, with peak current up to 0.5 A.
14 PDA output Totem-pole low-side driver for N-channel MOSFETs or Darlingtons, active high, with peak current up to 0.5 A.
15 GND power_in Ground reference for all thresholds and outputs except the PD and PU outputs.
16 PUC output Open-collector high-voltage high-side driver, active low, with output voltage rated from −0.3 V to 50 V and +200 mA continuous output current.
17 PUB output Open-collector high-voltage high-side driver, active low, with output voltage rated from −0.3 V to 50 V and +200 mA continuous output current.
18 PUA output Open-collector high-voltage high-side driver, active low, with output voltage rated from −0.3 V to 50 V and +200 mA continuous output current.
19 VCC power_in Supply pin for the device, specified for 10 V to 18 V with an absolute maximum of 20 V; outputs are held off below the 7.5 V undervoltage lockout and it should be bypassed with 0.1 µF.
20 TACH-OUT output Tachometer output producing a fixed-width 5 V pulse on each Hall state change, whose average is proportional to speed, with a high level of 4.7-5.3 V and a low level of 0.2 V max.
21 RC-BRAKE passive Tachometer timing node (pulse width T ≈ 0.67 RT CT, with RT 10 kΩ-500 kΩ and CT 1 nF-100 nF) that enters brake mode when pulled below the 0.8-1.2 V brake threshold.
22 QUAD SEL input Selects two-quadrant chopping when low and four-quadrant chopping when high, with thresholds of 0.8 V to 3.0 V.
23 OV-COAST input Overvoltage shutdown and/or coast input with an inhibit threshold of 1.65-1.85 V, drivable by TTL, 5 V CMOS, or 12 V CMOS.
24 SSTART passive Soft-start capacitor pin that clamps the error amplifier output and has a restart threshold of 0.1-0.3 V, with a 51 kΩ resistor from VREF recommended to ensure switching.
25 RC-OSC passive Oscillator timing node with frequency ≈ 2/(ROSC × COSC), where the ramp is about 1.2 V peak-to-peak centered near 1.6 V and frequency should stay below 500 kHz.
26 PWM IN input PWM comparator input compared against E/A OUT, which can be connected to RC-OSC for voltage-mode PWM, with input current of 0 to 30 µA when driven to 2.5 V.
27 E/A IN(-) input Error amplifier inverting input with input current of −5.0 µA to 5.0 µA when driven to 2.5 V, and which biases the error amplifier off when held above E/A IN(+).
28 E/A IN(+) input Error amplifier non-inverting input with input current of −5.0 µA to 5.0 µA when driven to 2.5 V and input offset of ±10 mV over a 0 V to 3 V common-mode range.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-28-300mil
Category Motor Driver ICs
Pins 28

CAD (KiCad official)

  • Symbol: UC2625MDWREP
  • Footprint: Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm
  • 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
  • 3D model files: uc2625mdwrep-etched.step / uc2625mdwrep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); uc2625mdwrep.step / uc2625mdwrep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 17c4943a718814ef, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF