component
AD7825BRZ
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADCs), SOIC-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownAD7825BRZ
Analog Devices · Analog To Digital Converters (ADCs) · SOIC-24-300mil
AD7825BRZ from Analog Devices, in a SOIC-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DB2 | tri_state | Data output line that is normally held in high impedance and driven onto the data bus when both RD and CS go active low. |
| 2 | DB1 | tri_state | Data output line that is normally held in high impedance and driven onto the data bus when both RD and CS go active low. |
| 3 | DB0 | tri_state | Data output line that is normally held in high impedance and driven onto the data bus when both RD and CS go active low. |
| 4 | CONVST | input | Convert start logic input that starts an 8-bit conversion on its falling edge, and if logic low at the end of a conversion the part powers down. |
| 5 | CS | input | Chip select logic input that enables the parallel port, needed when the ADC shares a data bus; both RD and CS must be low to enable the data bus. |
| 6 | RD | input | Read logic input that takes the output buffers out of high impedance and drives data onto the bus, internally gated with CS. |
| 7 | DGND | power_in | Digital ground, the ground reference for digital circuitry. |
| 8 | EOC | output | End-of-conversion logic output that indicates a finished conversion and can interrupt a microcontroller or latch data into a gate array. |
| 9 | A1 | input | Channel address input; the address of the next multiplexer channel must be present when RD goes low. |
| 10 | A0 | input | Channel address input; the address of the next multiplexer channel must be present when RD goes low. |
| 11 | PD | input | Power-down logic input; bringing it low places the part in power-down mode and bringing it high again powers the ADC up. |
| 12 | VIN4 | input | Analog input channel 4 with a span of 2.5 V (VDD = 5 V) or 2 V (VDD = 3 V), positionable within AGND to VDD using VMID. |
| 13 | VIN3 | input | Analog input channel 3 with a span of 2.5 V (VDD = 5 V) or 2 V (VDD = 3 V), positionable within AGND to VDD using VMID. |
| 14 | VIN2 | input | Analog input channel 2 with a span of 2.5 V (VDD = 5 V) or 2 V (VDD = 3 V), positionable within AGND to VDD using VMID. |
| 15 | VIN1 | input | Analog input channel 1 with a span of 2.5 V (VDD = 5 V) or 2 V (VDD = 3 V), positionable within AGND to VDD using VMID. |
| 16 | VMID | input | If connected, centers the analog input span anywhere in the range AGND to VDD (default 1.25 V at 5 V, 1 V at 3 V when unconnected). |
| 17 | VREF IN/OUT | power_in | Analog reference pin that accepts an external reference (2.45 V to 2.55 V) or provides the on-chip 2.5 V reference, which may be left unconnected or decoupled to AGND with 0.1 µF. |
| 18 | VDD | power_in | Positive supply voltage, 3 V ± 10% or 5 V ± 10%. |
| 19 | AGND | power_in | Analog ground, the reference for the track-and-hold, comparators, reference circuit and multiplexer. |
| 20 | DB7 | tri_state | Data output line that is normally held in high impedance and driven onto the data bus when both RD and CS go active low. |
| 21 | DB6 | tri_state | Data output line that is normally held in high impedance and driven onto the data bus when both RD and CS go active low. |
| 22 | DB5 | tri_state | Data output line that is normally held in high impedance and driven onto the data bus when both RD and CS go active low. |
| 23 | DB4 | tri_state | Data output line that is normally held in high impedance and driven onto the data bus when both RD and CS go active low. |
| 24 | DB3 | tri_state | Data output line that is normally held in high impedance and driven onto the data bus when both RD and CS go active low. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-24-300mil |
| Category | Data Converters |
| Pins | 24 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Signal to (Noise + Distortion) Ratio | SNDR | 48 | dB | fIN = 30 kHz, fSAMPLE = 2 MHz | 3 | ||
| Total Harmonic Distortion | THD | -55 | dB | fIN = 30 kHz, fSAMPLE = 2 MHz | 3 | ||
| Peak Harmonic or Spurious Noise | -55 | dB | fIN = 30 kHz, fSAMPLE = 2 MHz | 3 | |||
| Integral Nonlinearity | INL | -0.75 | 0.75 | LSB | 3 | ||
| Differential Nonlinearity | DNL | -0.75 | 0.75 | LSB | 3 | ||
| Gain Error | -2 | 2 | LSB | 3 | |||
| Offset Error | -1 | 1 | LSB | 3 | |||
| VIN1 to VIN8 Input Voltage | 0 | 5.5 | V | VDD = 5 V ± 10%, input voltage span = 2.5 V; max printed as VDD | 3 | ||
| VMID Input Voltage (5 V) | 1.25 | V | VDD = 5 V ± 10%, default VMID = 1.25 V; max printed as VDD − 1.25 V | 3 | |||
| VMID Input Voltage (3 V) | 1 | V | VDD = 3 V ± 10%, default VMID = 1 V; max printed as VDD − 1 V | 3 | |||
| VIN Input Leakage Current | -1 | 1 | μA | 3 | |||
| VIN Input Capacitance | 15 | pF | 3 | ||||
| VREF IN/OUT Input Voltage Range | 2.45 | 2.55 | V | 2.5 V ± 2% | 3 | ||
| VREF IN/OUT Input Current | 1 | 100 | μA | 3 | |||
| On-chip Reference Error | -50 | 50 | mV | Nominal 2.5 V | 3 | ||
| On-chip Reference Temperature Coefficient | 50 | ppm/°C | 3 | ||||
| Input High Voltage | VINH | 2.4 | V | VDD = 5 V ± 10% | 3 | ||
| Input Low Voltage | VINL | 0.8 | V | VDD = 5 V ± 10% | 3 | ||
| Input High Voltage | VINH | 2 | V | VDD = 3 V ± 10% | 3 | ||
| Input Low Voltage | VINL | 0.4 | V | VDD = 3 V ± 10% | 3 | ||
| Logic Input Current | IIN | -1 | 1 | μA | 10 nA typical, VIN = 0 V to VDD | 3 | |
| Logic Input Capacitance | CIN | 10 | pF | 3 | |||
| Output High Voltage | VOH | 4 | V | ISOURCE = 200 μA, VDD = 5 V ± 10% | 4 | ||
| Output High Voltage | VOH | 2.4 | V | ISOURCE = 200 μA, VDD = 3 V ± 10% | 4 | ||
| Output Low Voltage | VOL | 0.4 | V | ISINK = 200 μA, VDD = 5 V ± 10% | 4 | ||
| Output Low Voltage | VOL | 0.2 | V | ISINK = 200 μA, VDD = 3 V ± 10% | 4 | ||
| High Impedance Leakage Current | -1 | 1 | μA | 4 | |||
| High Impedance Capacitance | 10 | pF | 4 | ||||
| Track-and-Hold Acquisition Time | 200 | ns | See Circuit Description section | 4 | |||
| Conversion Time | 420 | ns | 4 | ||||
| Power Supply Rejection | -1 | 1 | LSB | VDD ± 10% | 4 | ||
| Supply Voltage (5 V) | VDD | 4.5 | 5.5 | V | 5 V ± 10%; for specified performance | 4 | |
| Supply Voltage (3 V) | VDD | 2.7 | 3.3 | V | 3 V ± 10%; for specified performance | 4 | |
| Supply Current, Normal Operation | IDD | 8 | 12 | mA | Normal operation | 4 | |
| Supply Current, Power-Down | IDD | 0.2 | 5 | μA | Logic inputs = 0 V or VDD | 4 | |
| Power Dissipation, Normal Operation | 24 | 36 | mW | VDD = 3 V | 4 | ||
| Power Dissipation, Power-Down 200 kSPS | 9.58 | mW | VDD = 3 V, 200 kSPS | 4 | |||
| Power Dissipation, Power-Down 500 kSPS | 23.94 | mW | VDD = 3 V, 500 kSPS | 4 | |||
| Conversion time | t1 | 420 | ns | Conversion time | 5 | ||
| Minimum CONVST pulse width | t2 | 20 | ns | Minimum CONVST pulse width | 5 | ||
| Time between rising edge of RD and next falling edge of convert start | t3 | 30 | ns | Minimum time between the rising edge of RD and the next falling edge of convert start | 5 | ||
| EOC pulse width | t4 | 70 | 110 | ns | EOC pulse width | 5 | |
| RD rising edge to EOC pulse high | t5 | 10 | ns | RD rising edge to EOC pulse high | 5 | ||
| CS to RD setup time | t6 | 0 | ns | CS to RD setup time | 5 | ||
| CS to RD hold time | t7 | 0 | ns | CS to RD hold time | 5 | ||
| Minimum RD pulse width | t8 | 30 | ns | Minimum RD pulse width | 5 | ||
| Data access time after RD low | t9 | 10 | ns | VDD = 5 V ± 10%; 20 ns max for 3 V ± 10% | 5 | ||
| Data access time after RD low (3 V) | t9 | 20 | ns | VDD = 3 V ± 10% | 5 | ||
| Bus relinquish time after RD high | t10 | 5 | 20 | ns | Bus relinquish time after RD high | 5 | |
| Address setup time before falling edge of RD | t11 | 10 | ns | 5 | |||
| Address hold time after falling edge of RD | t12 | 15 | ns | 5 | |||
| Time between new channel selection and convert start | t13 | 200 | ns | Minimum time between new channel selection and convert start | 5 | ||
| Power-up time using on-chip reference | tPOWER UP | 25 | μs | Power-up time from rising edge of CONVST using on-chip reference | 5 | ||
| Power-up time using external reference | tPOWER UP | 1 | μs | Power-up time from rising edge of CONVST using external 2.5 V reference | 5 | ||
| VDD to AGND | -0.3 | 7 | V | TA = 25°C | 6 | ||
| VDD to DGND | -0.3 | 7 | V | TA = 25°C | 6 | ||
| Analog Input Voltage to AGND (VIN1 to VIN8) | -0.3 | V | Max printed as VDD + 0.3 V; TA = 25°C | 6 | |||
| Operating Temperature Range (B Version) | -40 | 85 | °C | Industrial | 6 | ||
| Storage Temperature Range | -65 | 150 | °C | 6 | |||
| Junction Temperature | 150 | °C | 6 | ||||
| SOIC Package Power Dissipation | 450 | mW | SOIC package | 6 | |||
| SOIC θJA Thermal Impedance | θJA | 75 | °C/W | SOIC package | 6 |
CAD (KiCad official)
- Symbol:
AD7825BRZ - Footprint:
Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm - 3D model: SOIC-24-300mil (KiCad packages3D, STEP)
- 3D model files:
ad7825brz-etched.step/ad7825brz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7825brz.step/ad7825brz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
5957039edf3c2cfb, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).