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Contents

README

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PJM60N20TE

PJSEMI · MOSFETs · TO-252

PJM60N20TE from PJSEMI, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate. Insulated MOSFET gate; VGS(th) = 0.4-1 V (typ 0.65 V). Absolute maximum VGS = ±12 V. Drive at VGS = 4.5 V or higher for full enhancement (RDS(on) ~ 4.9 mΩ @ 25 A).
2 D passive Drain. Connected to the tab of the TO-252 package. V(BR)DSS = 20 V min, ID = 60 A continuous (IDM = 240 A pulsed). Primary heat-conduction path via the tab.
3 S passive Source. MOSFET source terminal; also anode of the intrinsic body diode (VSD ≤ 1.2 V @ IS = 30 A, IS max = 60 A). Reference for VGS and VDS.

Key specifications

Parameter Value
Manufacturer PJSEMI
Package TO-252
Category Transistors/Thyristors
Pins 3

Ordering variants

Same part, different packaging or reel option.

  • PJM60N20TE

CAD (KiCad official)

  • Symbol: PJM60N20TE
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PJSEMI datasheet (None pp, sha256 66b3d1c84e848f6f, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF