component

CD40103BDR

Public Made by Adom

by adom

lingxingic Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD40103BDR

lingxingic · Counters, Dividers · SOP-16

CD40103BDR from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CP input Clock input; the counter decrements on each LOW-to-HIGH (positive-going) clock transition.
2 MR input Asynchronous master reset input, active LOW; when LOW it clears the counter to its maximum count (decimal 255) regardless of the other inputs.
3 TE input Terminal enable input, active LOW; counting is inhibited while this input is HIGH.
4 P0 input Jam input 0 (least significant bit of the 8-bit preset word), loaded into the counter when PE or PL is LOW.
5 P1 input Jam input 1 of the 8-bit preset word, loaded into the counter when PE or PL is LOW.
6 P2 input Jam input 2 of the 8-bit preset word, loaded into the counter when PE or PL is LOW.
7 P3 input Jam input 3 of the 8-bit preset word, loaded into the counter when PE or PL is LOW.
8 GND power_in Ground (0 V) reference for all voltages.
9 PL input Asynchronous preset enable input, active LOW; when LOW, data at P0 to P7 is forced asynchronously into the counter regardless of the state of PE, TE or CP.
10 P4 input Jam input 4 of the 8-bit preset word, loaded into the counter when PE or PL is LOW.
11 P5 input Jam input 5 of the 8-bit preset word, loaded into the counter when PE or PL is LOW.
12 P6 input Jam input 6 of the 8-bit preset word, loaded into the counter when PE or PL is LOW.
13 P7 input Jam input 7 (most significant bit of the 8-bit preset word), loaded into the counter when PE or PL is LOW.
14 TC output Terminal count output, active LOW; goes LOW when the count reaches zero (if TE is LOW) and remains LOW for one full clock period.
15 PE input Synchronous preset enable input, active LOW; data at P0 to P7 is clocked into the counter on the next LOW-to-HIGH CP transition regardless of TE.
16 VCC power_in Positive supply voltage; recommended operating range is 2.0 V to 6.0 V referenced to GND.

Key specifications

Parameter Value
Manufacturer lingxingic
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 9
input clamping current IIK -20 20 mA VI<-0.5V or VI>VCC+0.5V 9
output clamping current IOK -20 20 mA VO<-0.5V or VO>VCC+0.5V 9
output current IO -25 25 mA VO=-0.5V to VCC+0.5V 9
supply current ICC 50 mA 9
ground current IGND -50 mA 9
storage temperature Tstg -65 150 ℃ 9
total power dissipation Ptot 500 mW 9
soldering temperature TL 260 ℃ 10s; SOP/TSSOP 9
supply voltage VCC 2 5 6 V 9
input voltage VI 0 V 9
output voltage VO 0 V 9
input transition rise and fall rate Δt/ΔV 625 ns/V VCC=2.0V 9
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC=4.5V 9
input transition rise and fall rate Δt/ΔV 83 ns/V VCC=6.0V 9
ambient temperature Tamb -40 125 ℃ 9
HIGH-level input voltage VIH 1.5 1.2 V Tamb=25℃; VCC=2.0V 10
HIGH-level input voltage VIH 3.15 2.4 V Tamb=25℃; VCC=4.5V 10
HIGH-level input voltage VIH 4.2 3.2 V Tamb=25℃; VCC=6.0V 10
LOW-level input voltage VIL 0.8 0.5 V Tamb=25℃; VCC=2.0V 10
LOW-level input voltage VIL 2.1 1.35 V Tamb=25℃; VCC=4.5V 10
LOW-level input voltage VIL 2.8 1.8 V Tamb=25℃; VCC=6.0V 10
HIGH-level output voltage VOH 1.9 2 V Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V 10
HIGH-level output voltage VOH 4.4 4.5 V Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V 10
HIGH-level output voltage VOH 5.9 6 V Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=6.0V 10
HIGH-level output voltage VOH 3.98 4.32 V Tamb=25℃; VI=VIH or VIL; IO=-4.0mA; VCC=4.5V 10
HIGH-level output voltage VOH 5.48 5.81 V Tamb=25℃; VI=VIH or VIL; IO=-5.2mA; VCC=6.0V 10
LOW-level output voltage VOL 0 0.1 V Tamb=25℃; VI=VIH or VIL; IO=20uA; VCC=2.0V 10
LOW-level output voltage VOL 0.15 0.26 V Tamb=25℃; VI=VIH or VIL; IO=4.0mA; VCC=4.5V 10
LOW-level output voltage VOL 0.16 0.26 V Tamb=25℃; VI=VIH or VIL; IO=5.2mA; VCC=6.0V 10
input leakage current II -1 1 uA Tamb=25℃; VI=VCC or GND; VCC=6.0V 10
supply current ICC 8 uA Tamb=25℃; VI=VCC or GND; IO=0A; VCC=6.0V 10
HIGH-level input voltage VIH 1.5 V Tamb=-40℃ to +125℃; VCC=2.0V 12
HIGH-level input voltage VIH 3.15 V Tamb=-40℃ to +125℃; VCC=4.5V 12
HIGH-level input voltage VIH 4.2 V Tamb=-40℃ to +125℃; VCC=6.0V 12
LOW-level input voltage VIL 0.5 V Tamb=-40℃ to +125℃; VCC=2.0V 12
LOW-level input voltage VIL 1.35 V Tamb=-40℃ to +125℃; VCC=4.5V 12
LOW-level input voltage VIL 1.8 V Tamb=-40℃ to +125℃; VCC=6.0V 12
HIGH-level output voltage VOH 1.9 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V 12
HIGH-level output voltage VOH 4.4 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V 12
HIGH-level output voltage VOH 5.9 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-20uA; VCC=6.0V 12
HIGH-level output voltage VOH 3.7 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-4.0mA; VCC=4.5V 12
HIGH-level output voltage VOH 5.2 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-5.2mA; VCC=6.0V 12
LOW-level output voltage VOL 0.1 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=20uA; VCC=2.0V 12
LOW-level output voltage VOL 0.4 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=4.0mA; VCC=4.5V 12
input leakage current II -1 1 uA Tamb=-40℃ to +125℃; VI=VCC or GND; VCC=6.0V 12
supply current ICC 160 uA Tamb=-40℃ to +125℃; VI=VCC or GND; IO=0A; VCC=6.0V 12
maximum frequency fmax 3 10 MHz see Figure 6; VCC=2.0V; Tamb=25℃ 14
maximum frequency fmax 15 29 MHz see Figure 6; VCC=4.5V; Tamb=25℃ 14
maximum frequency fmax 18 35 MHz see Figure 6; VCC=6.0V; Tamb=25℃ 14
maximum frequency fmax 2 MHz see Figure 6; VCC=2.0V; Tamb=-40℃ to +125℃ 18
maximum frequency fmax 10 MHz see Figure 6; VCC=4.5V; Tamb=-40℃ to +125℃ 18
maximum frequency fmax 12 MHz see Figure 6; VCC=6.0V; Tamb=-40℃ to +125℃ 18

CAD (KiCad official)

  • Symbol: CD40103BDR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd40103bdr-etched.step / cd40103bdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40103bdr.step / cd40103bdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (26 pp, sha256 d9416bbec0900a57, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF