component
DAC7558IRHBR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDAC7558IRHBR
Texas Instruments · Digital To Analog Converters (DAC) · QFN-32-EP(5x5)
DAC7558IRHBR from Texas Instruments, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VFBA | input | DAC A amplifier sense input, to be connected at the output node of channel A's amplifier for feedback. |
| 2 | VOUTA | output | Analog output voltage from DAC A, rail-to-rail with a 0 V to VREF output range. |
| 3 | VOUTB | output | Analog output voltage from DAC B, rail-to-rail with a 0 V to VREF output range. |
| 4 | VFBB | input | DAC B amplifier sense input, to be connected at the output node of channel B's amplifier for feedback. |
| 5 | VFBC | input | DAC C amplifier sense input, to be connected at the output node of channel C's amplifier for feedback. |
| 6 | VOUTC | output | Analog output voltage from DAC C, rail-to-rail with a 0 V to VREF output range. |
| 7 | VOUTD | output | Analog output voltage from DAC D, rail-to-rail with a 0 V to VREF output range. |
| 8 | VFBD | input | DAC D amplifier sense input, to be connected at the output node of channel D's amplifier for feedback. |
| 9 | VREF2 | input | Positive reference voltage input for DAC C and DAC D; reference input range is 0 V to VDD. |
| 10 | SDO | output | Serial data output for daisy-chain operation, valid 10 ns after the SCLK falling edge at VDD = 2.7 V to 3.6 V and at VDD = 3.6 V to 5.5 V. |
| 11 | IOVDD | power_in | I/O voltage supply input for the digital interface; the logic is compatible with 1.8 V to 5.5 V logic levels. |
| 12 | DGND | power_in | Digital ground reference for the serial interface and digital logic. |
| 13 | SDIN | input | Serial data input; data is clocked in on SCLK with 5 ns setup and 4.5 ns hold time at VDD = 2.7 V to 5.5 V. |
| 14 | SCLK | input | Serial clock input, with a maximum SCLK frequency of 50 MHz at VDD = 2.7 V to 5.5 V. |
| 15 | SYNC | input | Frame synchronization input; the falling edge of the SYNC pulse indicates the start of a serial data frame shifted into the DAC7558. |
| 16 | VREF3 | input | Positive reference voltage input for DAC E and DAC F; reference input range is 0 V to VDD. |
| 17 | VFBE | input | DAC E amplifier sense input, to be connected at the output node of channel E's amplifier for feedback. |
| 18 | VOUTE | output | Analog output voltage from DAC E, rail-to-rail with a 0 V to VREF output range. |
| 19 | VOUTF | output | Analog output voltage from DAC F, rail-to-rail with a 0 V to VREF output range. |
| 20 | VFBF | input | DAC F amplifier sense input, to be connected at the output node of channel F's amplifier for feedback. |
| 21 | VFBG | input | DAC G amplifier sense input, to be connected at the output node of channel G's amplifier for feedback. |
| 22 | VOUTG | output | Analog output voltage from DAC G, rail-to-rail with a 0 V to VREF output range. |
| 23 | VOUTH | output | Analog output voltage from DAC H, rail-to-rail with a 0 V to VREF output range. |
| 24 | VFBH | input | DAC H amplifier sense input, to be connected at the output node of channel H's amplifier for feedback. |
| 25 | VREF4 | input | Positive reference voltage input for DAC G and DAC H; reference input range is 0 V to VDD. |
| 26 | DCEN | input | Daisy-chain enable input. |
| 27 | PD | input | Power-down input; the datasheet specifies per-channel power-down with under 2 µA supply current when powered down. |
| 28 | VDD | power_in | Analog voltage supply input, 2.7 V to 5.5 V single supply. |
| 29 | AGND | power_in | Analog ground; the thermal pad must be connected to AGND. |
| 30 | RSTSEL | input | Reset select: when low, input coding is binary; when high, input coding is 2s complement, and the reset value is set by this pin together with RST. |
| 31 | RST | input | Asynchronous reset, active low; when low, all DAC channels reset to zero scale (RSTSEL = 0) or to midscale (RSTSEL = 1). |
| 32 | VREF1 | input | Positive reference voltage input for DAC A and DAC B; reference input range is 0 V to VDD. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-32-EP(5x5) |
| Category | Data Acquisition |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
DAC7558IRHBR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
dac7558irhbr-etched.step/dac7558irhbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac7558irhbr.step/dac7558irhbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (32 pp, sha256
e51e6810ea3878db, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).