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CD4017BE

Public Made by Adom

by adom

lingxingic Counters, Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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CD4017BE

lingxingic · Counters, Dividers · DIP-16

CD4017BE from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q5 output Spike-free decoded active-HIGH counter output for state 5, with the supply range of 3 V to 15 V referenced to VSS.
2 Q1 output Spike-free decoded active-HIGH counter output for state 1, with the supply range of 3 V to 15 V referenced to VSS.
3 Q0 output Spike-free decoded active-HIGH counter output for state 0; MR going HIGH forces Q0 HIGH and Q1 to Q9 LOW.
4 Q2 output Spike-free decoded active-HIGH counter output for state 2, with the supply range of 3 V to 15 V referenced to VSS.
5 Q6 output Spike-free decoded active-HIGH counter output for state 6, with the supply range of 3 V to 15 V referenced to VSS.
6 Q7 output Spike-free decoded active-HIGH counter output for state 7, with the supply range of 3 V to 15 V referenced to VSS.
7 Q3 output Spike-free decoded active-HIGH counter output for state 3, with the supply range of 3 V to 15 V referenced to VSS.
8 VSS power_in Ground reference (0 V) for all voltages; the recommended VDD range of 3 V to 15 V is referenced to VSS.
9 Q8 output Spike-free decoded active-HIGH counter output for state 8, with the supply range of 3 V to 15 V referenced to VSS.
10 Q4 output Spike-free decoded active-HIGH counter output for state 4, with the supply range of 3 V to 15 V referenced to VSS.
11 Q9 output Spike-free decoded active-HIGH counter output for state 9, with the supply range of 3 V to 15 V referenced to VSS.
12 Q5-9 output Active-LOW carry output that is LOW while the counter is in states 5 to 9, used to drive CP0 of the next counter when cascading.
13 CP1 input Clock input that is HIGH-to-LOW edge-triggered and advances the counter only while CP0 is HIGH; unused inputs must be tied to VDD, VSS or another input.
14 CP0 input Clock input that is LOW-to-HIGH edge-triggered and advances the counter only while CP1 is LOW; unused inputs must be tied to VDD, VSS or another input.
15 MR input Asynchronous master reset input; a HIGH resets the counter to zero independent of the clock inputs, and unused inputs must be tied to VDD, VSS or another input.
16 VDD power_in Supply voltage with a recommended range of 3 V to 15 V referenced to VSS, and an absolute maximum of 18 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VDD -0.5 18 V 7
DC input current IIK -10 10 mA any one input 7
input voltage VI -0.5 V all inputs 7
storage temperature Tstg -65 150 ℃ 7
total power dissipation Ptot 500 mW 7
device dissipation per output transistor P 100 mW 7
soldering temperature TL 245 ℃ 10s DIP 7
supply voltage VDD 3 15 V 7
ambient temperature Tamb -40 85 ℃ in free air 7
clock input frequency fCL 2.5 MHz VDD=5V 7
clock input frequency fCL 5 MHz VDD=10V 7
clock input frequency fCL 5.5 MHz VDD=15V 7
clock pulse width tw 200 ns VDD=5V 7
clock pulse width tw 90 ns VDD=10V 7
clock pulse width tw 60 ns VDD=15V 7
clock inhibit setup time ts 230 ns VDD=5V 7
clock inhibit setup time ts 100 ns VDD=10V 7
clock inhibit setup time ts 70 ns VDD=15V 7
reset pulse width tRW 260 ns VDD=5V 7
reset pulse width tRW 110 ns VDD=10V 7
reset pulse width tRW 60 ns VDD=15V 7
reset removal time trec 400 ns VDD=5V 7
reset removal time trec 280 ns VDD=10V 7
reset removal time trec 150 ns VDD=15V 7
supply current IDD 0.04 5 uA VIN 0,5 V; VDD 5 V; Tamb=25℃ 8
supply current IDD 0.04 10 uA VIN 0,10 V; VDD 10 V; Tamb=25℃ 8
supply current IDD 0.04 20 uA VIN 0,15 V; VDD 15 V; Tamb=25℃ 8
LOW-level output current IOL 0.51 1 mA VO 0.4 V; VIN 0,5 V; VDD 5 V; Tamb=25℃ 8
LOW-level output current IOL 1.3 2.6 mA VO 0.5 V; VIN 0,10 V; VDD 10 V; Tamb=25℃ 8
LOW-level output current IOL 3.4 6.8 mA VO 1.5 V; VIN 0,15 V; VDD 15 V; Tamb=25℃ 8
HIGH-level output current IOH -0.51 -1 mA VO 4.6 V; VIN 0,5 V; VDD 5 V; Tamb=25℃ 8
HIGH-level output current IOH -1.6 -3.2 mA VO 2.5 V; VIN 0,5 V; VDD 5 V; Tamb=25℃ 8
HIGH-level output current IOH -1.3 -2.6 mA VO 9.5 V; VIN 0,10 V; VDD 10 V; Tamb=25℃ 8
HIGH-level output current IOH -3.4 -6.8 mA VO 13.5 V; VIN 0,15 V; VDD 15 V; Tamb=25℃ 8
LOW-level output voltage VOL 0 0.05 V VIN 0,5 V; VDD 5 V; Tamb=25℃ 8
HIGH-level output voltage VOH 4.95 5 V VIN 0,5 V; VDD 5 V; Tamb=25℃ 8
HIGH-level output voltage VOH 9.95 10 V VIN 0,10 V; VDD 10 V; Tamb=25℃ 8
HIGH-level output voltage VOH 14.95 15 V VIN 0,15 V; VDD 15 V; Tamb=25℃ 8
LOW-level input voltage VIL 1.5 V VO 0.5,4.5 V; VDD 5 V; Tamb=25℃ 8
LOW-level input voltage VIL 3 V VO 1,9 V; VDD 10 V; Tamb=25℃ 8
LOW-level input voltage VIL 4 V VO 1.5,13.5 V; VDD 15 V; Tamb=25℃ 8
HIGH-level input voltage VIH 3.5 V VO 0.5,4.5 V; VDD 5 V; Tamb=25℃ 8
HIGH-level input voltage VIH 7 V VO 1,9 V; VDD 10 V; Tamb=25℃ 8
HIGH-level input voltage VIH 11 V VO 1.5,13.5 V; VDD 15 V; Tamb=25℃ 8
input leakage current II -0.1 0.1 uA VIN 0,15 V; VDD 15 V; Tamb=25℃ 8
supply current IDD 5 uA VIN 0,5 V; VDD 5 V; Tamb=-40℃ 8
supply current IDD 10 uA VIN 0,10 V; VDD 10 V; Tamb=-40℃ 8
supply current IDD 20 uA VIN 0,15 V; VDD 15 V; Tamb=-40℃ 8
supply current IDD 150 uA VIN 0,5 V; VDD 5 V; Tamb=+85℃ 8
supply current IDD 300 uA VIN 0,10 V; VDD 10 V; Tamb=+85℃ 8
supply current IDD 600 uA VIN 0,15 V; VDD 15 V; Tamb=+85℃ 8
propagation delay time CP0, CP1 to Q0-Q9 tPHL, tPLH 325 650 ns CP0, CP1 to Q0 to Q9; VDD=5V; see Figure 7 9
propagation delay time CP0, CP1 to Q0-Q9 tPHL, tPLH 135 270 ns CP0, CP1 to Q0 to Q9; VDD=10V; see Figure 7 9
propagation delay time CP0, CP1 to Q0-Q9 tPHL, tPLH 85 170 ns CP0, CP1 to Q0 to Q9; VDD=15V; see Figure 7 9
maximum clock frequency fCL 2.5 5 MHz VDD=5V; see Figure 8 9
maximum clock frequency fCL 5 10 MHz VDD=10V; see Figure 8 9
maximum clock frequency fCL 5.5 11 MHz VDD=15V; see Figure 8 9

CAD (KiCad official)

  • Symbol: CD4017BE
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4017be-etched.step / cd4017be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4017be.step / cd4017be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (14 pp, sha256 527e9a8997b56b8c, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF