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Contents

README

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MAX17048G+T10

Maxim Integrated · Battery Management · DFN-8-EP(2x2)

MAX17048G+T10 from Maxim Integrated, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CTG passive CTG is to be connected to ground.
2 CELL input CELL connects to the positive battery terminal and is not internally connected on the MAX17048.
3 VDD power_in VDD is the power-supply input, to be bypassed with 0.1µF to GND, and on the MAX17048 it is the voltage sense input connected to the positive battery terminal.
4 GND power_in GND is the ground pin, connected to the negative battery terminal.
5 ALRT output ALRT is an open-drain, active-low alert output that can optionally connect to a microcontroller interrupt input.
6 QSTRT input QSTRT is the quick-start input that allows hardware reset of the device and must be connected to GND if not used.
7 SCL input SCL is the I2C clock input with an internal pulldown (IPD) for sensing disconnection.
8 SDA bidirectional SDA is the open-drain I2C data input/output with an internal pulldown (IPD) for sensing disconnection.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Maxim Integrated
Package DFN-8-EP(2x2)
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
CELL to GND -0.3 12 V CELL to GND 2
All other pins to GND -0.3 6 V All other pins to GND 2
Continuous sink current, SDA, ALRT 20 mA SDA, ALRT 2
Operating temperature range -40 85 °C 2
Storage temperature range -55 125 °C 2
Lead temperature (soldering, 10s) 300 °C TDFN only, soldering 10s 2
Soldering temperature (reflow) 260 °C Reflow 2
Supply voltage VDD 2.5 4.5 V 2
Fuel-gauge SOC reset (VRESET register) configuration range VRST 2.28 3.48 V Configuration range, in 40mV steps 2
Fuel-gauge SOC reset (VRESET register) trimmed VRST 2.85 3 3.15 V Trimmed at 3V 2
Data I/O pins SCL, SDA, ALRT -0.3 5.5 V 2
Supply current, sleep mode IDD0 0.5 2 µA Sleep mode, TA ≤ +50°C 2
Supply current, hibernate mode, reset comparator disabled IDD0 3 5 µA Hibernate mode, reset comparator disabled (VRESET.Dis = 1) 2
Supply current, active mode IDD1 23 40 µA Active mode 2
Time base accuracy tERR -3.5 1 3.5 % Active, hibernate modes 2
Voltage error VERR -7.5 7.5 mV/cell VCELL = 3.6V, TA = +25°C 2
Voltage error VERR -20 20 mV/cell 2
Voltage-measurement range (MAX17048 VDD pin) 2.5 5 V MAX17048: VDD pin 2
Bus low-detection current IPD 0.2 0.4 µA VSDA = VSCL = 0.4V 2
Bus low-detection timeout tSLEEP 1.75 2.5 s 2
SCL clock frequency fSCL 0 400 kHz 3
Data hold time tHD:DAT 0 0.9 µs 3

CAD (KiCad official)

  • Symbol: MAX17048G+T10
  • Footprint: Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm
  • 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: max17048g-t10-etched.step / max17048g-t10-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max17048g-t10.step / max17048g-t10.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Maxim Integrated datasheet (19 pp, sha256 70dc8eef0e012276, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF